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| Multiformat Video Encoder Six 14-Bit Noise Shaped Video(R) DACs ADV7344 FEATURES 74.25 MHz 20-/30-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p), and 240M (1035i) 6 Noise Shaped Video (NSV) 14-bit video DACs 16x (216 MHz) DAC oversampling for SD 8x (216 MHz) DAC oversampling for ED 4x (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 YCrCb (ED and HD) 4:4:4 RGB (SD, ED, and HD) Multiformat video output support Composite (CVBS) and S-Video (Y/C) Component YPrPb (SD, ED, and HD) Component RGB (SD, ED, and HD) Macrovision(R) Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Simultaneous SD and ED/HD operation EIA/CEA-861B compliance support Programmable features Luma and chroma filter responses Vertical blanking interval (VBI) Subcarrier frequency (FSC) and phase Luma delay Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern generation On-board voltage reference (optional external input) Serial MPU interface with dual I2C(R) and SPI(R) compatibility 3.3 V analog operation 1.8 V digital operation 3.3 V I/O operation Temperature range: -40C to +85C APPLICATIONS DVD recorders and players High definition Blu-ray DVD players HD-DVD players FUNCTIONAL BLOCK DIAGRAM DGND (2) VDD (2) SCL/ SDA/ ALSB/ MOSI SCLK SPI_SS SFL/ MISO AGND VAA GND_IO VDD_IO VBI DATA SERVICE INSERTION MPU PORT SUBCARRIER FREQUENCY LOCK (SFL) ADV7344 14-BIT DAC 1 DAC 1 10-BIT SD VIDEO DATA 4:2:2 TO 4:4:4 HD DDR DEINTERLEAVE ADD BURST PROGRAMMABLE CHROMINANCE FILTER RGB MULTIPLEXER RGB/YCrCb TO YUV MATRIX ADD SYNC PROGRAMMABLE LUMINANCE FILTER YUV TO YCrCb/ RGB SIN/COS DDS BLOCK 16x FILTER 14-BIT DAC 2 14-BIT DAC 3 14-BIT DAC 4 14-BIT DAC 5 DAC 2 16x FILTER DAC 3 R G/B 20-BIT ED/HD VIDEO DATA RGB ASYNC BYPASS YCbCr DAC 4 ED/HD INPUT DEINTERLEAVE PROGRAMMABLE HDTV FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL HDTV TEST PATTERN GENERATOR YCbCr TO RGB MATRIX DAC 5 4x FILTER 14-BIT DAC 6 DAC 6 POWER MANAGEMENT CONTROL VIDEO TIMING GENERATOR 16x/4x OVERSAMPLING DAC PLL REFERENCE AND CABLE DETECT RSET (2) RESET P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC CLKIN (2) PVDD PGND EXT_LF VREF COMP (2) Figure 1. Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights. Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. 06400-001 ADV7344 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Detailed Features .............................................................................. 4 General Description ......................................................................... 4 Specifications..................................................................................... 5 Power Supply and Voltage Specifications.................................. 5 Voltage Reference Specifications ................................................ 5 Input Clock Specifications .......................................................... 5 Analog Output Specifications..................................................... 6 Digital Input/Output Specifications........................................... 6 Digital Timing Specifications ..................................................... 7 MPU Port Timing Specifications ............................................... 8 Power Specifications .................................................................... 8 Video Performance Specifications ............................................. 9 Timing Diagrams............................................................................ 10 Absolute Maximum Ratings.......................................................... 17 Thermal Resistance .................................................................... 17 ESD Caution................................................................................ 17 Pin Configuration and Function Descriptions........................... 18 Typical Performance Characteristics ........................................... 20 MPU Port Description................................................................... 25 I2C Operation.............................................................................. 25 SPI Operation.............................................................................. 26 Register Map Access....................................................................... 27 Register Programming............................................................... 27 Subaddress Register (SR7 to SR0) ............................................ 27 Input Configuration ....................................................................... 44 Standard Definition Only.......................................................... 44 Enhanced Definition/High Definition Only .......................... 45 Simultaneous Standard Definition and Enhanced Definition/High Definition....................................................... 45 Enhanced Definition Only (at 54 MHz) ................................. 46 Output Configuration .................................................................... 47 Features ............................................................................................ 48 Output Oversampling ................................................................ 48 ED/HD Nonstandard Timing Mode........................................ 48 ED/HD Timing Reset ................................................................ 49 SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and Timing Reset ............................................................................... 49 SD VCR FF/RW Sync ................................................................ 50 Vertical Blanking Interval ......................................................... 50 SD Subcarrier Frequency Registers.......................................... 50 SD Noninterlaced Mode............................................................ 51 SD Square Pixel Mode ............................................................... 51 Filters............................................................................................ 52 ED/HD Test Pattern Color Controls ....................................... 53 Color Space Conversion Matrix ............................................... 53 SD Luma and Color Control..................................................... 54 SD Hue Adjust Control.............................................................. 55 SD Brightness Detect ................................................................. 55 SD Brightness Control............................................................... 55 SD Input Standard Auto Detection.......................................... 55 Double Buffering ........................................................................ 56 Programmable DAC Gain Control .......................................... 56 Gamma Correction .................................................................... 56 ED/HD Sharpness Filter and Adaptive Filter Controls......... 58 ED/HD Sharpness Filter and Adaptive Filter Application Examples...................................................................................... 59 SD Digital Noise Reduction...................................................... 60 SD Active Video Edge Control ................................................. 62 External Horizontal and Vertical Synchronization Control ........................................................... 63 Low Power Mode........................................................................ 64 Cable Detection .......................................................................... 64 DAC Auto Power-Down............................................................ 64 Pixel and Control Port Readback............................................. 64 Reset Mechanism........................................................................ 64 Printed Circuit Board Layout and Design .................................. 65 DAC Configurations.................................................................. 65 Voltage Reference ....................................................................... 65 Video Output Buffer and Optional Output Filter.................. 65 Printed Circuit Board (PCB) Layout ....................................... 66 Typical Application Circuit....................................................... 68 Appendix 1--Copy Generation Management System .............. 69 SD CGMS .................................................................................... 69 ED CGMS.................................................................................... 69 HD CGMS................................................................................... 69 CGMS CRC Functionality ........................................................ 69 Rev. 0 | Page 2 of 88 ADV7344 Appendix 2--SD Wide Screen Signaling .....................................72 Appendix 3--SD Closed Captioning............................................73 Appendix 4--Internal Test Pattern Generation ..........................74 SD Test Patterns...........................................................................74 ED/HD Test Patterns ..................................................................74 Appendix 5--SD Timing................................................................75 Appendix 6--HD Timing ..............................................................80 Appendix 7--Video Output Levels...............................................81 SD YPrPb Output Levels--SMPTE/EBU N10........................81 ED/HD YPrPb Output Levels ...................................................82 SD/ED/HD RGB Output Levels................................................83 SD Output Plots ..........................................................................84 Appendix 8--Video Standards ......................................................85 Outline Dimensions........................................................................87 Ordering Guide ...........................................................................87 REVISION HISTORY 10/06--Revision 0: Initial Version Rev. 0 | Page 3 of 88 ADV7344 DETAILED FEATURES High definition (HD) programmable features (720p/1080i/1035i) 4x oversampling (297 MHz) Internal test pattern generator Color and black bar, hatch, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS (720p/1080i) and CGMS Type B (720p/1080i) Dual data rate (DDR) input support EIA/CEA-861B compliance support Enhanced definition (ED) programmable features (525p/625p) 8x oversampling (216 MHz output) Internal test pattern generator Color and black bar, hatch, flat field/frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) CGMS (525p/625p) and CGMS Type B (525p) Dual data rate (DDR) input support EIA/CEA-861B compliance support Standard definition (SD) programmable features 16x oversampling (216 MHz) Internal test pattern generator Color and black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAFTM filter with programmable gain/attenuation PrPb SSAFTM Separate pedestal control on component and composite/S-Video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 Copy generation management system (CGMS) Wide screen signaling Closed captioning EIA/CEA-861B compliance support The ADV7344 has a 30-bit pixel input port that can be configured in a variety of ways. SD video formats are supported over a SDR interface and ED/HD video formats are supported over SDR and DDR interfaces. Pixel data can be supplied in either the YCrCb or RGB color spaces. The ADV7344 also supports embedded EAV/SAV timing codes, external video synchronization signals, and I2C and SPI communication protocols. In addition, simultaneous SD and ED/HD input and output is supported. 216 MHz (SD and ED) and 297 MHz (HD) oversampling ensures that external output filtering is not required, while full-drive DACs ensure that external output buffering is not required. Cable detection and DAC auto power-down features keep power consumption to a minimum. Table 1 lists the video standards directly supported by the ADV7344. Table 1. Standards Directly Supported by the ADV7344 1 Resolution 720 x 240 720 x 288 720 x 480 720 x 576 720 x 480 720 x 576 720 x 483 720 x 483 720 x 483 720 x 576 720 x 483 720 x 576 1920 x 1035 1920 x 1035 1280 x 720 1280 x 720 I/P 2 P P I I I I P P P P P P I I P P Frame Rate (Hz) 59.94 50 29.97 25 29.97 25 59.94 59.94 59.94 50 59.94 50 30 29.97 60, 50, 30, 25, 24 23.97, 59.94, 29.97 30, 25 29.97 30, 25, 24 23.98, 29.97 24 Clock Input (MHz) 27 27 27 27 24.54 29.5 27 27 27 27 27 27 74.25 74.1758 74.25 74.1758 Standard ITU-R BT.601/656 ITU-R BT.601/656 NTSC Square Pixel PAL Square Pixel SMPTE 293M BTA T-1004 ITU-R BT.1358 ITU-R BT.1358 ITU-R BT.1362 ITU-R BT.1362 SMPTE 240M SMPTE 240M SMPTE 296M SMPTE 296M GENERAL DESCRIPTION The ADV7344 is a high speed, digital-to-analog video encoder in a 64-pin LQFP package. Six high speed, NSV, 3.3 V, 14-bit video DACs provide support for composite (CVBS), S-Video (YC), and component (YPrPb/RGB) analog outputs in either standard definition (SD), enhanced definition (ED) or high definition (HD) video formats. 1920 x 1080 1920 x 1080 1920 x 1080 1920 x 1080 1920 x 1080 1 2 I I P P P 74.25 74.1758 74.25 74.1758 74.25 SMPTE 274M SMPTE 274M SMPTE 274M SMPTE 274M ITU-R BT.709-5 Other standards are supported in the ED/HD nonstandard timing mode. I = interlaced, P = progressive. Rev. 0 | Page 4 of 88 ADV7344 SPECIFICATIONS POWER SUPPLY AND VOLTAGE SPECIFICATIONS All specifications TMIN to TMAX (-40C to +85C), unless otherwise noted. Table 2. Parameter SUPPLY VOLTAGES VDD VDD_IO PVDD VAA POWER SUPPLY REJECTION RATIO Conditions Min 1.71 2.97 1.71 2.6 Typ 1.8 3.3 1.8 3.3 0.002 Max 1.89 3.63 1.89 3.465 Unit V V V V %/% VOLTAGE REFERENCE SPECIFICATIONS All specifications TMIN to TMAX (-40C to +85C), unless otherwise noted. Table 3. Parameter Internal Reference Range, VREF External Reference Range, VREF External VREF Current 1 1 Conditions Min 1.186 1.15 Typ 1.248 1.235 10 Max 1.31 1.31 Unit V V A External current required to overdrive internal VREF. INPUT CLOCK SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (-40C to +85C), unless otherwise noted. Table 4. Parameter fCLKIN_A fCLKIN_A fCLKIN_A fCLKIN_B fCLKIN_B CLKIN_A High Time, t9 CLKIN_A Low Time, t10 CLKIN_B High Time, t9 CLKIN_B Low Time, t10 CLKIN_A Peak-to-Peak Jitter Tolerance CLKIN_B Peak-to-Peak Jitter Tolerance 1 Conditions 1 SD/ED ED (at 54 MHz) HD ED HD Min Typ 27 54 74.25 27 74.25 Max 40 40 40 40 2 2 Unit MHz MHz MHz MHz MHz % of one clock cycle % of one clock cycle % of one clock cycle % of one clock cycle ns ns SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition. Rev. 0 | Page 5 of 88 ADV7344 ANALOG OUTPUT SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. VREF = 1.235 V (driven externally). All specifications TMIN to TMAX (-40C to +85C), unless otherwise noted. Table 5. Parameter Full Drive Output Current (Full-Scale) 1 Low Drive Output Current (Full-Scale) 2 DAC-to-DAC Matching Output Compliance, VOC Output Capacitance, COUT Analog Output Delay 3 DAC Analog Output Skew Conditions RSET = 510 , RL = 37.5 RSET = 4.12 k, RL = 300 DAC 1 to DAC 6 DAC 1, DAC 2, DAC 3 DAC 4, DAC 5, DAC 6 DAC 1, DAC 2, DAC 3 DAC 4, DAC 5, DAC 6 DAC 1, DAC 2, DAC 3 DAC 4, DAC 5, DAC 6 Min 33 4.1 0 10 6 8 6 2 1 Typ 34.6 4.3 1.0 Max 37 4.5 1.4 Unit mA mA % V pF pF ns ns ns ns 1 2 Applicable to full drive capable DACs only, that is, DAC 1, DAC 2, DAC 3. Applicable to all DACs. 3 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition. DIGITAL INPUT/OUTPUT SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (-40C to +85C), unless otherwise noted. Table 6. Parameter Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIN Input Capacitance, CIN Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance Conditions Min 2.0 Typ Max 0.8 10 4 ISOURCE = 400 A ISINK = 3.2 mA VIN = 0.4 V, 2.4 V 2.4 0.4 1.0 4 Unit V V A pF V V A pF VIN = VDD_IO Rev. 0 | Page 6 of 88 ADV7344 DIGITAL TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (-40C to +85C), unless otherwise noted. Table 7. Parameter VIDEO DATA AND VIDEO CONTROL PORT 2, 3 Data Setup Time, t11 4 Conditions 1 SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) Min 2.1 2.3 2.3 1.7 1.0 1.1 1.1 1.0 2.1 2.3 1.7 1.0 1.1 1.0 12 10 4.0 3.5 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Hold Time, t124 Control Setup Time, t114 Control Hold Time, t124 Digital Output Access Time, t134 Digital Output Hold Time, t144 PIPELINE DELAY 5 SD1 CVBS/YC Outputs (2x) CVBS/YC Outputs (16x) Component Outputs (2x) Component Outputs (16x) ED1 Component Outputs (1x) Component Outputs (8x) HD1 Component Outputs (1x) Component Outputs (4x) 1 2 SD oversampling disabled SD oversampling enabled SD oversampling disabled SD oversampling enabled ED oversampling disabled ED oversampling enabled HD oversampling disabled HD oversampling enabled 68 67 78 84 41 46 40 44 clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. Video data: C[9:0], Y[9:0], and S[9:0]. 3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design. Rev. 0 | Page 7 of 88 ADV7344 MPU PORT TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (-40C to +85C), unless otherwise noted. Table 8. Parameter MPU PORT, I2C MODE 1 SCL Frequency SCL High Pulse Width, t1 SCL Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDA, SCL Rise Time, t6 SDA, SCL Fall Time, t7 Setup Time (Stop Condition), t8 MPU PORT, SPI MODE1 SCLK Frequency SPI_SS to SCLK Setup Time, t1 SCLK High Pulse Width, t2 SCLK Low Pulse Width, t3 Data Access Time after SCLK Falling Edge, t4 Data Setup Time prior to SCLK Rising Edge, t5 Data Hold Time after SCLK Rising Edge, t6 SPI_SS to SCLK Hold Time, t7 SPI_SS to MISO High Impedance, t8 1 Conditions See Figure 19. Min 0 0.6 1.3 0.6 0.6 100 Typ Max 400 Unit kHz s s s s ns ns ns s MHz ns ns ns ns ns ns ns ns 300 300 0.6 See Figure 20. 0 20 50 50 20 0 0 40 10 35 Guaranteed by characterization. POWER SPECIFICATIONS Table 9. Parameter NORMAL POWER MODE 1, 2 IDD 3 Conditions SD only (16x oversampling) ED only (8x oversampling) 4 HD only (4x oversampling)4 SD (16x oversampling) and ED (8x oversampling) SD (16x oversampling) and HD (4x oversampling) 3 DACs enabled (ED/HD only) 6 DACs enabled (SD only and simultaneous modes ) SD only, ED only or HD only modes Simultaneous modes Min Typ 90 65 91 95 122 1 124 140 5 10 5 0.3 0.2 0.1 Max Unit mA mA mA mA mA mA mA mA mA mA A A A A IDD_IO IAA 5 IPLL SLEEP MODE IDD IAA IDD_IO IPLL 1 2 RSET1 = 510 (DAC 1, DAC 2 and DAC 3 operating in full drive mode). RSET2 = 4.12 k (DAC 4, DAC 5, and DAC 6 operating in low drive mode). 75% color bar test pattern applied to pixel data pins. 3 IDD is the continuous current required to drive the digital core. 4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes. 5 IAA is the total current required to supply all DACs including the VREF circuitry. Rev. 0 | Page 8 of 88 ADV7344 VIDEO PERFORMANCE SPECIFICATIONS Table 10. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity 1 +ve Differential Nonlinearity1 -ve STANDARD DEFINTION (SD) MODE Luminance Nonlinearity Differential Gain Differential Phase SNR SNR ENHANCED DEFINITION (ED) MODE Luma Bandwidth Chroma Bandwidth HIGH DEFINITION (HD) MODE Luma Bandwidth Chroma Bandwidth 1 Conditions Min Typ 14 3 4 1 3.2 1.7 1.4 0.2 0.2 0.3 64.5 79.5 12.5 5.8 30 13.75 Max Unit Bits LSBs LSBs LSBs LSBs LSBs LSBs % % Degrees dB dB MHz MHz MHz MHz RSET1 = 510 , RL1 = 37.5 RSET2 = 4.12 k, RL2 = 300 RSET1 = 510 , RL1 = 37.5 RSET2 = 4.12 k, RL2 = 300 RSET1 = 510 , RL1 = 37.5 RSET2 = 4.12 k, RL2 = 300 NTSC NTSC Luma ramp Flat field full bandwidth Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value. For -ve DNL, the actual step value lies below the ideal step value. Rev. 0 | Page 9 of 88 ADV7344 TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 13: t9 = Clock high time t10 = Clock low time t11 = Data setup time CLKIN_A t12 = Data hold time t13 = Control output access time t14 = Control output hold time In addition, refer to Table 31 for the ADV7344 input configuration. t9 CONTROL INPUTS S_HSYNC, S_VSYNC t10 t12 IN SLAVE MODE S9 TO S0/Y9 TO Y0* Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 CONTROL OUTPUTS t13 IN MASTER/SLAVE MODE t14 *SELECTED BY SUBADDRESS 0x01, BIT 7. 06400-002 Figure 2. SD Only, 8-/10-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000) CLKIN_A t9 CONTROL INPUTS S_HSYNC, S_VSYNC t10 t12 IN SLAVE MODE S9 TO S0/Y9 TO Y0* Y0 Y1 Y2 Y3 Y9 TO Y0/C9 TO C0* Cb0 Cr0 Cb2 Cr2 t11 CONTROL OUTPUTS t13 IN MASTER/SLAVE MODE 06400-003 t14 *SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 3. SD Only, 16-/20-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000) CLKIN_A t9 CONTROL INPUTS S_HSYNC, S_VSYNC t10 t12 Y9 TO Y2/Y9 TO Y0 G0 G1 G2 C9 TO C2/C9 TO C0 B0 B1 B2 t11 S9 TO S2/S9 TO S0 CONTROL OUTPUTS 06400-004 R0 R1 R2 t14 t13 Figure 4. SD Only, 24-/30-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000) Rev. 0 | Page 10 of 88 ADV7344 CLKIN_A t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y0 Cb0 t10 t12 Y9 TO Y2/Y9 TO Y0 C9 TO C2/C9 TO C0 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y4 Cb4 Y5 Cr4 t11 CONTROL OUTPUTS t13 06400-005 t14 Figure 5. ED/HD-SDR Only, 16-/20-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 001) CLKIN_A t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y0 t10 t12 Y9 TO Y2/Y9 TO Y0 C9 TO C2/C9 TO C0 Y1 Cb1 Y2 Cb2 Y3 Cb3 Y4 Cb4 Y5 Cb5 Cb0 t11 S9 TO S2/S9 TO S0 CONTROL OUTPUTS 06400-006 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 t14 t13 Figure 6. ED/HD-SDR Only, 24-/30-Bit, 4:4:4 YCrCb Pixel Input Mode (Input Mode 001) CLKIN_A t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK G0 B0 t10 t12 Y9 TO Y2/Y9 TO Y0 C9 TO C2/C9 TO C0 G1 B1 G2 B2 G3 B3 G4 B4 G5 B5 t11 S9 TO S2/S9 TO S0 CONTROL OUTPUTS 06400-007 R0 R1 R2 R3 R4 R5 t14 t13 Figure 7. ED/HD-SDR Only, 24-/30-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001) Rev. 0 | Page 11 of 88 ADV7344 CLKIN_A* t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Cb0 Y0 t10 Y9 TO Y2/Y9 TO Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 CONTROL OUTPUTS t12 t11 t12 t13 t14 *LUMA/CHROMACLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. 06400-008 Figure 8. ED/HD-DDR Only, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 010) CLKIN_A* t9 Y9 TO Y2/Y9 TO Y0 3FF 00 t10 00 XY Cb0 Y0 Cr0 Y1 t11 CONTROL OUTPUTS t12 t11 t12 t13 *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 9. ED/HD-DDR Only, 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010) CLKIN_B t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y0 Cb0 t10 t12 06400-009 t14 Y9 TO Y2/Y9 TO Y0 C9 TO C2/C9 TO C0 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y4 Cb4 Y5 Cr4 Y6 Cb6 ED/HD INPUT t11 CLKIN_A t9 CONTROL INPUTS S_HSYNC, S_VSYNC Cb0 t10 t12 SD INPUT 06400-010 S9 TO S2/S9 TO S0 Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 Figure 10. SD, ED/HD-SDR Input Mode, 16-/20-Bit, 4:2:2 ED/HD and 8-/10-Bit, SD Pixel Input Mode (Input Mode 011) Rev. 0 | Page 12 of 88 ADV7344 CLKIN_B P_HSYNC, P_VSYNC, P_BLANK Cb0 t9 t10 CONTROL INPUTS ED/HD INPUT Y0 Cr0 Y1 Cb2 Y2 Cr2 Y9 TO Y2/Y9 TO Y0 t11 t12 t11 t12 CLKIN_A t9 CONTROL INPUTS S_HSYNC, S_VSYNC t10 t12 SD INPUT 06400-011 S9 TO S2/S9 TO S0 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 Figure 11. SD, ED/HD-DDR Input Mode, 8-/10-Bit, 4:2:2 ED/HD and 8-/10-Bit, SD Pixel Input Mode (Input Mode 100) CLKIN_A CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK t9 t10 Y9 TO Y2/Y9 TO Y0 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 CONTROL OUTPUTS t12 t13 t14 06400-012 Figure 12. ED Only (at 54 MHz), 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 111) CLKIN_A t9 Y9 TO Y2/Y9 TO Y0 3FF t10 00 00 XY Cb0 Y0 Cr0 Y1 t11 CONTROL OUTPUTS t12 t13 t14 06400-013 Figure 13. ED Only (at 54 MHz), 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111) Rev. 0 | Page 13 of 88 ADV7344 Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y9 TO Y2/Y9 TO Y0 Y0 Y1 Y2 Y3 C9 TO C2/C9 TO C0 Cb0 Cr0 Cb2 Cr2 b a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 14. ED-SDR, 16-/20-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y9 TO Y2/Y9 TO Y0 Cb0 Y0 Cr0 Y1 b a = 32 CLOCK CYCLES FOR 525p a = 24 CLOCK CYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLOCK CYCLES FOR 525p b(MIN) = 264 CLOCK CYCLES FOR 625p c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. 06400-015 Figure 15. ED-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Rev. 0 | Page 14 of 88 06400-014 ADV7344 Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y9 TO Y2/Y9 TO Y0 Y0 Y1 Y2 Y3 C9 TO C2/C9 TO C0 Cb0 Cr0 Cb2 Cr2 b a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 16. HD-SDR, 16-/20-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y9 TO Y2/Y9 TO Y0 Cb0 Y0 Cr0 Y1 b a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. 06400-016 06400-017 Figure 17. HD-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Rev. 0 | Page 15 of 88 ADV7344 S_HSYNC S_VSYNC S9 TO S0/Y9 TO Y0* Cb Y Cr Y *SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 18. SD Input Timing Diagram (Timing Mode 1) t3 SDA t5 t3 t6 SCL t1 t2 t7 t4 2 t8 Figure 19. MPU Port Timing Diagram (I C Mode) SPI_SS t1 SCLK t2 06400-019 06400-018 PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES t3 t5 t6 D3 D2 D1 D0 X X X X X X X X t7 MOSI X D7 D6 D5 D4 MISO X X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 Figure 20. MPU Port Timing Diagram (SPI Mode) Rev. 0 | Page 16 of 88 06400-020 t4 t8 ADV7344 ABSOLUTE MAXIMUM RATINGS Table 11. Parameter1 VAA to AGND VDD to DGND PVDD to PGND VDD_IO to GND_IO VAA to VDD VDD to PVDD VDD_IO to VDD AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to GND_IO Digital Input Voltage to GND_IO Analog Outputs to AGND Storage Temperature Range (TS) Junction Temperature (TJ) Lead Temperature (Soldering, 10 sec) 1 Rating -0.3 V to +3.9 V -0.3 V to +2.3 V -0.3 V to +2.3 V -0.3 V to +3.9 V -0.3 V to +2.2 V -0.3 V to +0.3 V -0.3 V to +2.2 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to VDD_IO + 0.3 V -0.3 V to VAA -65C to +150C 150C 260C The ADV7344 is a high performance integrated circuit with an ESD rating of <1 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 12. Thermal Resistance1 Package Type 64-Lead LQFP 1 JA 47 JC 11 Unit C/W Values are based on a JEDEC 4-layer test board. The ADV7344 is a Pb-free product. The lead finish is 100% pure Sn electroplate. The device is RoHS compliant, suitable for Pbfree applications up to 255C (5C) IR reflow (JEDEC STD-20). It is backward-compatible with conventional SnPb soldering processes. The electroplated Sn coating can be soldered with Sn/Pb solder paste at conventional reflow temperatures of 220C to 235C. Analog output short circuit to any power supply or common can be of an indefinite duration. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 17 of 88 ADV7344 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS S_HSYNC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 PIN 1 47 46 45 44 VDD_IO Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 S_VSYNC CLKIN_B GND_IO DGND VDD S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 1 2 3 4 5 6 7 8 9 SFL/MISO RSET1 VREF COMP1 DAC 1 DAC 2 DAC 3 VAA AGND DAC 4 DAC 5 DAC 6 RSET2 COMP2 PVDD EXT_LF1 ADV7344 TOP VIEW (Not to Scale) 43 42 41 40 39 38 37 36 35 34 33 VDD 10 DGND 11 Y8 12 Y9 13 C0 14 C1 15 C2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCL/MOSI ALSB/SPI_SS EXT_LF2 SDA/SCLK P_HSYNC P_VSYNC P_BLANK CLKIN_A PGND C3 C4 C5 C6 C7 C8 C9 Figure 21. Pin Configuration Table 13. Pin Function Descriptions Pin No. 13, 12, 9 to 2 29 to 25, 18 to 14 62 to 58, 55 to 51 30 63 50 Mnemonic Y9 to Y0 C9 to C0 S9 to S0 CLKIN_A CLKIN_B S_HSYNC Input/ Output I I I I I I/O Description 10-Bit Pixel Port (Y9 to Y0). Y0 is the LSB. Refer to Table 31 for input modes. 10-Bit Pixel Port (C9 to C0). C0 is the LSB. Refer to Table 31 for input modes. 10-Bit Pixel Port (S9 to S0). S0 is the LSB. Refer to Table 31 for input modes. Pixel Clock Input for HD only (74.25 MHz), ED 1 only (27 MHz or 54 MHz) or SD only (27 MHz). Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a 74.25 MHz reference clock for HD operation. SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD horizontal synchronization signal. See the External Horizontal and Vertical Synchronization Control section. SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control section. ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical Synchronization Control section. ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization Control section. ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section. Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is used to drive the color subcarrier DDS system, timing reset, or subcarrier reset. This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive operation (for example, into a 37.5 load), a 510 resistor must be connected from RSET1 to AGND. For low drive operation (for example, into a 300 load), a 4.12 k resistor must be connected from RSET1 to AGND. This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 k resistor must be connected from RSET2 to AGND. Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to VAA. Rev. 0 | Page 18 of 88 49 22 23 24 48 47 S_VSYNC P_HSYNC P_VSYNC P_BLANK SFL/MISO RSET1 I/O I I I I/O I 36 45, 35 RSET2 COMP1, COMP2 I O 06400-021 ADV7344 Pin No. 44, 43, 42 39, 38, 37 21 20 19 46 41 10, 56 1 34 33 31 32 40 11, 57 64 1 2 Mnemonic DAC 1, DAC 2, DAC 3 DAC 4, DAC 5, DAC 6 SCL/MOSI SDA/SCLK ALSB/SPI_SS VREF VAA VDD VDD_IO PVDD EXT_LF1 EXT_LF2 PGND AGND DGND GND_IO Input/ Output O O I I/O I P P P P I I G G G G Description DAC Outputs. Full and low drive capable DACs. DAC Outputs. Low drive only capable DACs. Multifunctional Pin: I2C Clock Input/SPI Data Input. Multifunctional Pin: I2C Data Input/Output. Also, SPI clock input. Multifunctional Pin: This signal sets up the LSB 2 of the MPU I2C address. Also, SPI slave select. Optional External Voltage Reference Input for DACs or Voltage Reference Output. Analog Power Supply (3.3 V). Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. Input/Output Digital Power Supply (3.3 V). PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. External Loop Filter for On-Chip PLL 1. External Loop Filter for On-Chip PLL 2. PLL Ground Pin. Analog Ground Pin. Digital Ground Pin. Input/Output Supply Ground Pin. ED = enhanced definition = 525p and 625p. LSB = least significant bit. In the ADV7344, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. Rev. 0 | Page 19 of 88 ADV7344 TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 0.5 -10 -20 0 -0.5 GAIN (dB) 1.0 Y RESPONSE IN ED 8x OVERSAMPLING MODE GAIN (dB) -30 -40 -50 -60 -70 06400-022 -1.0 -1.5 -2.0 -2.5 06400-025 -80 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 -3.0 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 22. ED 8x Oversampling, PrPb Filter (Linear) Response ED Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 -10 -20 Figure 25. ED 8x Oversampling, Y Filter Response (Focus on Pass Band) HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 10 0 -10 -20 -30 GAIN (dB) GAIN (dB) 06400-023 -30 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 0 18.5 37.0 55.5 74.0 92.5 FREQUENCY (MHz) 111.0 129.5 148.0 Figure 23. ED 8x Oversampling, PrPb Filter (SSAF) Response Y RESPONSE IN ED 8x OVERSAMPLING MODE 0 -10 -20 Figure 26. HD 4x Oversampling, PrPb (SSAF) Filter Response (4:2:2 Input) HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE 0 -10 -20 -30 GAIN (dB) GAIN (dB) -30 -40 -50 -60 -70 06400-024 -40 -50 -60 -70 -80 -90 10 20 30 40 50 60 70 80 90 100 110 120 130 140 FREQUENCY (MHz) 06400-027 -80 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 -100 Figure 24. ED 8x Oversampling, Y Filter Response Figure 27. HD 4x Oversampling, PrPb (SSAF) Filter Response (4:4:4 Input) Rev. 0 | Page 20 of 88 06400-026 -100 ADV7344 10 0 -10 Y RESPONSE IN HD 4x OVERSAMPLING MODE 0 -10 -20 -30 -40 -50 -60 -70 -30 -40 -50 -60 -70 -80 -90 0 18.5 37.0 55.5 74.0 92.5 FREQUENCY (MHz) 111.0 129.5 148.0 06400-028 MAGNITUDE (dB) -20 GAIN (dB) -100 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 28. HD 4x Oversampling, Y Filter Response 3.0 1.5 0 Y PASS BAND IN HD 4x OVERSAMPLING MODE Figure 31. SD PAL, Luma Low-Pass Filter Response 0 -10 -20 -30 -40 -50 -60 -70 06400-029 GAIN (dB) -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 27.750 30.063 32.375 34.688 37.000 39.312 41.625 43.937 46.250 FREQUENCY (MHz) MAGNITUDE (dB) -1.5 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 29. HD 4x Oversampling, Y Filter Response (Focus on Pass Band) Figure 32. SD NTSC, Luma Notch Filter Response 0 -10 -20 -30 -40 -50 -60 -70 0 -10 -20 -30 -40 -50 -60 06400-030 MAGNITUDE (dB) MAGNITUDE (dB) 0 2 4 6 8 FREQUENCY (MHz) 10 12 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 30. SD NTSC, Luma Low-Pass Filter Response Figure 33. SD PAL, Luma Notch Filter Response Rev. 0 | Page 21 of 88 06400-033 -70 06400-032 06400-031 ADV7344 Y RESPONSE IN SD OVERSAMPLING MODE 0 -10 MAGNITUDE (dB) 4 5 -20 GAIN (dB) 3 -30 -40 -50 -60 -70 06400-034 2 1 0 -80 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 0 1 2 3 4 FREQUENCY (MHz) 5 6 7 Figure 34. SD, 16x Oversampling, Y Filter Response 0 -10 -20 -30 -40 -50 -60 -70 Figure 37. SD Luma SSAF Filter, Programmable Gain 1 0 MAGNITUDE (dB) MAGNITUDE (dB) -1 -2 -3 -4 06400-035 0 2 4 6 8 FREQUENCY (MHz) 10 12 0 1 2 3 4 FREQUENCY (MHz) 5 6 7 Figure 35. SD Luma SSAF Filter Response up to 12 MHz 4 2 0 MAGNITUDE (dB) Figure 38. SD Luma SSAF Filter, Programmable Attenuation 0 -10 -20 -30 -40 -50 -60 -70 -2 -4 -6 -8 -10 06400-036 0 1 2 3 4 FREQUENCY (MHz) 5 6 7 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 36. SD Luma SSAF Filter, Programmable Responses Figure 39. SD Luma CIF Low-Pass Filter Response Rev. 0 | Page 22 of 88 06400-039 -12 MAGNITUDE (dB) 06400-038 -5 06400-037 -1 ADV7344 0 -10 -20 -30 -40 -50 -60 -70 0 -10 -20 -30 -40 -50 -60 -70 MAGNITUDE (dB) MAGNITUDE (dB) 0 2 4 6 8 FREQUENCY (MHz) 06400-040 10 12 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 40. SD Luma QCIF Low-Pass Filter Response 0 -10 -20 -30 -40 -50 -60 -70 Figure 43. SD Chroma 1.3 MHz Low-Pass Filter Response 0 -10 -20 -30 -40 -50 -60 -70 MAGNITUDE (dB) MAGNITUDE (dB) 0 2 4 6 8 FREQUENCY (MHz) 10 06400-041 12 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 41. SD Chroma 3.0 MHz Low-Pass Filter Response 0 -10 -20 -30 -40 -50 -60 -70 Figure 44. SD Chroma 1.0 MHz Low-Pass Filter Response 0 -10 -20 -30 -40 -50 -60 -70 MAGNITUDE (dB) MAGNITUDE (dB) 06400-042 0 2 4 6 8 FREQUENCY (MHz) 10 12 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 42. SD Chroma 2.0 MHz Low-Pass Filter Response Figure 45. SD Chroma 0.65 MHz Low-Pass Filter Response Rev. 0 | Page 23 of 88 06400-045 06400-044 06400-043 ADV7344 0 -10 -20 -30 -40 -50 -60 -70 0 -10 -20 -30 -40 -50 -60 -70 06400-046 MAGNITUDE (dB) MAGNITUDE (dB) 0 2 4 6 8 FREQUENCY (MHz) 10 12 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 46. SD Chroma CIF Low-Pass Filter Response Figure 47. SD Chroma QCIF Low-Pass Filter Response Rev. 0 | Page 24 of 88 06400-047 ADV7344 MPU PORT DESCRIPTION Devices such as a microprocessor can communicate with the ADV7344 through one of the following protocols: * * 2-wire serial (I2C-compatible) bus 4-wire serial (SPI-compatible) bus line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition occurs when the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADV7344 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period, the user should issue only a start condition, a stop condition, or a stop condition followed by a start condition. If an invalid subaddress is issued by the user, the ADV7344 does not issue an acknowledge and does return to the idle condition. If the user utilizes the auto-increment method of addressing the encoder and exceeds the highest subaddress, the following actions are taken: * In read mode, the highest subaddress register contents are output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition occurs when the SDA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7344, and the part returns to the idle condition. After power-up or reset, the MPU port is configured for I2C operation. SPI operation can be invoked at any time by following the procedure outlined in the SPI Operation section. I2C OPERATION The ADV7344 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV7344. Each slave device is recognized by a unique address. The ADV7344 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 48. The LSB either sets a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. A1 is controlled by setting the ALSB/SPI_SS pin of the ADV7344 to Logic 0 or Logic 1. 1 1 0 1 0 1 A1 X ADDRESS CONTROL SET UP BY ALSB/SPI_SS READ/WRITE CONTROL 0 1 WRITE READ 06400-048 Figure 48. ADV7344 Slave Address = 0xD4 or 0xD6 To control the various devices on the bus, use the following protocol. The master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit).The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data * Rev. 0 | Page 25 of 88 ADV7344 Figure 49 shows an example of data transfer for a write sequence and the start and stop conditions. Figure 50 shows bus write and read sequences. SDA S 9 1-7 8 START ADDR R/W ACK 9 1-7 8 SUBADDRESS ACK 1-7 DATA 8 9 ACK P STOP Figure 49. I2C Data Transfer WRITE SEQUENCE S SLAVE ADDR A(S) SUBADDR A(S) DATA A(S) LSB = 1 DATA A(S) P LSB = 0 READ SEQUENCE S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA A(M) 06400-049 SCL DATA A(M) P 06400-050 S = START BIT P = STOP BIT A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER Figure 50. I2C Read and Write Sequence SPI OPERATION The ADV7344 supports a 4-wire serial (SPI-compatible) bus connecting multiple peripherals. Two inputs, master out slave in (MOSI) and serial clock (SCLK), and one output, master in slave out (MISO), carry information between a master SPI peripheral on the bus and the ADV7344. Each slave device on the bus has a slave select pin that is connected to the master SPI peripheral by a unique slave select line. As such, slave device addressing is not required. To invoke SPI operation, a master SPI peripheral (for example, a microprocessor) should issue three low pulses on the ADV7344 ALSB/SPI_SS pin. When the encoder detects the third rising edge on the ALSB/SPI_SS pin, it automatically switches to SPI communication mode. The ADV7344 remains in SPI communication mode until a reset or power-down occurs. To control the ADV7344, use the following protocol for both read and write transactions. First, the master initiates a data transfer by driving and holding the ALSB/SPI_SS pin low. On the first SCLK rising edge after ALSB/SPI_SS has been driven low, the write command, defined as 0xD4, is written to the ADV7344 over the MOSI line. The second byte written to the MOSI line is interpreted as the starting subaddress. Data on the MOSI line is written MSB first and clocked on the rising edge of SCLK. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. The user can also access any unique subaddress register on a one-by-one basis. In a write data transfer, 8-bit data bytes are written to the ADV7344, MSB first, on the MOSI line immediately after the starting subaddress. The data bytes are clocked into the ADV7344 on the rising edge of SCLK. When all data bytes have been written, the master completes the transfer by driving and holding the ALSB/SPI_SS pin high. In a read data transfer, after the subaddress has been clocked in on the MOSI line, the ALSB/SPI_SS pin is driven and held high for at least one clock cycle. Then, the ALSB/SPI_SS pin is driven and held low again. On the first SCLK rising edge after ALSB/SPI_SS has been driven low, the read command, defined as 0xD5, is written, MSB first, to the ADV7344 over the MOSI line. Subsequently, 8-bit data bytes are read from the ADV7344, MSB first, on the MISO line. The data bytes are clocked out of the ADV7344 on the falling edge of SCLK. When all data bytes have been read, the master completes the transfer by driving and holding the ALSB/SPI_SS pin high. Rev. 0 | Page 26 of 88 ADV7344 REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV7344 via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines which register the next read or write operation accesses. All communication through the MPU port starts with an access to the subaddress register. A read/write operation is then performed from/to the target address, which increments to the next address until the transaction is complete. REGISTER PROGRAMMING Table 14 to Table 28 describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated. SUBADDRESS REGISTER (SR7 TO SR0) The subaddress register is an 8-bit write-only register. After the MPU port is accessed and a read/write operation is selected, the subaddress is set up. The subaddress register determines to or from which register the operation takes place. Table 14. Register 0x00 SR7 to SR0 0x00 Register Power Mode Register Bit Description Sleep Mode. With this control enabled, the current consumption is reduced to A level. All DACs and the internal PLL circuit are disabled. I2C registers can be read from and written to in sleep mode. PLL and Oversampling Control. This control allows the internal PLL circuit to be powered down and the oversampling to be switched off. DAC 3: Power on/off. DAC 2: Power on/off. DAC 1: Power on/off. DAC 6: Power on/off. DAC 5: Power on/off. DAC 4: Power on/off. 0 1 0 1 0 1 0 1 0 1 7 6 Bit Number 5432 1 0 0 1 0 1 0 1 Register Setting Sleep mode off. Sleep mode on. PLL on. PLL off. DAC 3 off. DAC 3 on. DAC 2 off. DAC 2 on. DAC 1 off. DAC 1 on. DAC 6 off. DAC 6 on. DAC 5 off. DAC 5 on. DAC 4 off. DAC 4 on. Reset Value 0x12 Rev. 0 | Page 27 of 88 ADV7344 Table 15. Register 0x01 to Register 0x09 SR7 to SR0 0x01 Register Mode Select Register Bit Description Reserved. DDR Clock Edge Alignment. Note: Only used for ED 1 and HD DDR modes. 7 6 Bit Number 5432 0 0 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 x x x x 0x05 0x06 0x07 0x08 0x09 1 2 1 0 1 0 1 0 0 Register Setting Chroma clocked in on rising clock edge; luma clocked in on falling clock edge. Reserved. Reserved. Luma clocked in on rising clock edge; chroma clocked in on falling clock edge. SD input only. ED/HD-SDR input only. ED/HD-DDR input only. SD and ED/HD-SDR. SD and ED/HD-DDR. Reserved. Reserved. ED only (at 54 MHz). Allows data to be applied to data ports in various configurations (SD feature only). Reset Value 0x00 Reserved. Input Mode. Note: See Reg. 0x30, Bits[7:3] for ED/HD format selection. 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Y/C/S Bus Swap. 0x02 Mode Register 0 Reserved. Test Pattern Black Bar. 2 Manual RGB Matrix Adjust. Sync on RGB. RGB/YPrPb Output Select. SD Sync Output Enable. 0 0 must be written to these bits. Disabled. Enabled. Disable manual RGB matrix adjust. Enable manual RGB matrix adjust. No sync. Sync on all RGB outputs. RGB component outputs. YPrPb component outputs. No sync output. Output SD syncs on S_HSYNC and S_VSYNC pins. No sync output. Output ED/HD syncs on S_HSYNC and S_VSYNC pins. 0x20 ED/HD Sync Output Enable. 0x03 0x04 ED/HD CSC Matrix 0 ED/HD CSC Matrix 1 x x x x x x x x x x x x x x x x x x x x LSBs for GY. LSBs for RV. LSBs for BU. LSBs for GV. LSBs for GU. Bits[9:2 ] for GY. Bits[9:2] for GU. Bits[9:2] for GV. Bits[9:2] for BU. Bits[9:2] for RV. 0x03 0xF0 x ED/HD CSC Matrix 2 ED/HD CSC Matrix 3 ED/HD CSC Matrix 4 ED/HD CSC Matrix 5 ED/HD CSC Matrix 6 x x x x x x x x x x x x x x x x x x x x x x x x x 0x4E 0x0E 0x24 0x92 0x7C ED = enhanced definition = 525p and 625p. Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD). Rev. 0 | Page 28 of 88 ADV7344 Table 16. Register 0x0A to Register 0x10 SR7 to SR0 0x0A Register DAC 4, DAC 5, DAC 6 Output Levels Bit Description Positive Gain to DAC Output Voltage. 7 0 0 0 ... 0 0 1 1 1 ... 1 0 0 0 ... 0 0 1 1 1 ... 1 6 0 0 0 ... 0 1 1 1 0 ... 1 0 0 0 ... 0 1 1 1 0 ... 1 5 0 0 0 ... 1 0 0 0 0 ... 1 0 0 0 ... 1 0 0 0 0 ... 1 Bit Number 4 3 0 0 0 0 0 0 ...... 1 1 0 0 0 0 0 0 0 0 ...... 1 1 0 0 0 0 0 0 ...... 1 1 0 0 0 0 0 0 0 0 ...... 1 1 2 0 0 0 ... 1 0 0 0 0 ... 1 0 0 0 ... 1 0 0 0 0 ... 1 1 0 0 1 ... 1 0 0 0 1 ... 1 0 0 1 ... 1 0 0 0 1 ... 1 0 0 1 0 ... 1 0 0 1 0 ... 1 0 1 0 ... 1 0 0 1 0 ... 1 0 1 Register Setting 0% +0.018% +0.036% ... +7.382% +7.5% -7.5% -7.382% -7.364% ... -0.018% 0% +0.018% +0.036% ... +7.382% +7.5% -7.5% -7.382% -7.364% ... -0.018% DAC 1 low power disabled DAC 1 low power enabled DAC 2 low power disabled DAC 2 low power enabled DAC 3 low power disabled DAC 3 low power enabled Cable detected on DAC 1 DAC 1 unconnected Cable detected on DAC 2 DAC 2 unconnected DAC auto power-down disable DAC auto power-down enable Reset Value 0x00 Negative Gain to DAC Output Voltage. 0x0B DAC 1, DAC 2, DAC 3 Output Levels Positive Gain to DAC Output Voltage. 0x00 Negative Gain to DAC Output Voltage. 0x0D DAC Power Mode DAC 1 Low Power Enable. DAC 2 Low Power Enable. DAC 3 Low Power Enable. Reserved. DAC 1 Cable Detect (Read Only). DAC 2 Cable Detect (Read Only). Reserved. Unconnected DAC Auto Power-Down. 0 0 1 Reserved. 0 0 0 0 0 0 0 0 0 0 1 0 1 0x00 0x10 Cable Detection 0 1 0 1 0x00 Rev. 0 | Page 29 of 88 ADV7344 Table 17. Register 0x12 to Register 0x17 SR7 to SR0 0x12 0x13 0x14 0x15 Register Pixel Port Readback (S Bus MSBs) Pixel Port Readback (Y Bus MSBs) Pixel Port Readback (C Bus MSBs) Pixel Port Readback (S, Y, and C Bus LSBs) Bit Description S[9:2] Readback. Y[9:2] Readback. C[9:2] Readback. C[1:0] Readback. Y[1:0] Readback. S[1:0] Readback. Reserved. P_BLANK. P_VSYNC. P_HSYNC. S_VSYNC. S_HSYNC. SFL/MISO. Reserved. Reserved. Software Reset. Reserved. x 0 0 0 0 1 0 0 0 0 0 0 Writing a 1 resets the device; this is a self-clearing bit 0x00 x x 7 x x x 6 x x x Bit Number 5432 xxxx xxxx xxxx x x 0 0 x x x Read only 0xXX x x 1 x x x x 0 x x x x Register Setting Read only Read only Read only Read only Reset Value 0xXX 0xXX 0xXX 0xXX 0x16 Control Port Readback 0x17 Software Reset Rev. 0 | Page 30 of 88 ADV7344 Table 18. Register 0x30 SR7 to SR0 0x30 Register ED/HD Mode Register 1 Bit Description ED/HD Output Standard. 7 6 Bit Number 5432 1 0 0 1 1 ED/HD Input Synchronization Format. ED/HD Input Mode. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 Register Setting EIA770.2 output. EIA770.3 output. EIA770.1 output. Output levels for full input range. Reserved. External HSYNC, VSYNC and field inputs 1. Embedded EAV/SAV codes. SMPTE 293M, ITU-BT.1358. Nonstandard timing mode. BTA-1004, ITU-BT.1362. ITU-BT.1358. ITU-BT.1362. SMPTE 296M-1, SMPTE 274M-2. SMPTE 296M-3. SMPTE 296M-4, SMPTE 274M-5. SMPTE 296M-6. SMPTE 296M-7, SMPTE 296M-8. SMPTE 240M. Reserved. Reserved. SMPTE 274M-4, SMPTE 274M-5. SMPTE 274M-6. SMPTE 274M-7, SMPTE 274M-8. SMPTE 274M-9. SMPTE 274M-10, SMPTE 274M-11. ITU-R BT.709-5. Reserved. Note ED HD Reset Value 0x00 525p @ 59.94 Hz 525p @ 59.94 Hz 625p @ 50 Hz 625p @ 50 Hz 720p @ 60/59.94 Hz 720p @ 50 Hz 720p @ 30/29.97 Hz 720p @ 25 Hz 720p @ 24/23.98 Hz 1035i @ 60/59.94 Hz 1080i @ 30/29.97 Hz 1080i @ 25 Hz 1080p @ 0/29.97 Hz 1080p @ 25 Hz 1080p @ 4/23.98 Hz 1080Psf @ 24 Hz 0010 10011-11111 1 Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6. Rev. 0 | Page 31 of 88 ADV7344 Table 19. Register 0x31 to Register 0x33 SR7 to SR0 0x31 Register ED/HD Mode Register 2 Bit Description ED/HD Pixel Data Valid. Reserved. ED/HD Test Pattern Enable. ED/HD Test Pattern Hatch/Field. ED/HD VBI Open. ED Only Undershoot Limiter. 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 7 6 Bit Number 5432 1 0 0 1 Register Setting Pixel data valid off. Pixel data valid on. HD test pattern off. HD test pattern on. Hatch. Field/frame. Disabled. Enabled. Disabled. -11 IRE. -6 IRE. -1.5 IRE. Disabled. Enabled. 0 clock cycles. 1 clock cycle. 2 clock cycles. 3 clock cycles. 4 clock cycles. 0 clock cycles. 1 clock cycle. 2 clock cycles. 3 clock cycles. 4 clock cycles. Disabled. Enabled. Disabled. Enabled. Cb after falling edge of HSYNC. Cr after falling edge of HSYNC. 0 must be written to this bit. 8-bit input. 10-bit input. Disabled. Enabled. 0 must be written to this bit. Disabled. Enabled. 4:4:4. 4:2:2. Disabled. Enabled. Reset Value 0x00 0 0 1 ED/HD Sharpness Filter. 0x32 ED/HD Mode Register 3 ED/HD Y Delay with Respect to Falling Edge of HSYNC. 0x00 ED/HD Color Delay with Respect to Falling Edge of HSYNC. ED/HD CGMS. ED/HD CGMS CRC. 0x33 ED/HD Mode Register 4 ED/HD Cr/Cb Sequence. Reserved. ED/HD Input Format. Sinc Compensation Filter on DAC 1, DAC 2, DAC 3. Reserved. ED/HD Chroma SSAF. ED/HD Chroma Input. ED/HD Double Buffering. 0x68 Rev. 0 | Page 32 of 88 ADV7344 Table 20. Register 0x34 to Register 0x35 SR7 to SR0 0x34 Register ED/HD Mode Register 5 Bit Description ED/HD Timing Reset. ED/HD HSYNC Control. 1 ED/HD VSYNC Control.1 ED/HD Blank Polarity. ED Macrovision Enable. Reserved. ED/HD VSYNC/Field Input. Horizontal/Vertical Counters. 2 0x35 ED/HD Mode Register 6 Reserved. ED/HD RGB Input Enable. ED/HD Sync on PrPb. ED/HD Color DAC Swap. ED/HD Gamma Correction Curve Select. ED/HD Gamma Correction Enable. ED/HD Adaptive Filter Mode. ED/HD Adaptive Filter Enable. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 Disabled. Enabled. Disabled. Enabled. DAC 2 = Pb, DAC 3 = Pr. DAC 2 = Pr, DAC 3 = Pb. Gamma Correction Curve A. Gamma Correction Curve B. Disabled. Enabled. Mode A. Mode B. Disabled. Enabled. 0 1 0 0 1 0 1 0 1 P_BLANK active high. P_BLANK active low. Macrovision disabled. Macrovision enabled. 0 must be written to this bit. 0 = field input. 1 = VSYNC input. Update field/line counter. Field/line counter free running. 0x00 7 6 Bit Number 5432 1 0 0 1 Register Setting Internal ED/HD timing counters enabled. Resets the internal ED/HD timing counters. HSYNC output control. VSYNC output control. Reset Value 0x48 0 1 1 2 Used in conjunction with ED/HD Sync in Subaddress 0x02, Bit 7, set to 1. When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. Rev. 0 | Page 33 of 88 ADV7344 Table 21. Register 0x36 to Register 0x43 SR7 to SR0 0x36 0x37 0x38 0x39 Register ED/HD Y Level 1 ED/HD Cr Level1 ED/HD Cb Level1 ED/HD Mode Register 7 Bit Description ED/HD Test Pattern Y Level. ED/HD Test Pattern Cr Level. ED/HD Test Pattern Cb Level. Reserved. ED/HD EIA/CEA-861B Synchronization Compliance. Reserved. ED/HD Sharpness Filter Gain, Value A. 7 x x x 6 x x x 5 x x x 0 1 0 0 0 0 ... 0 1 ... 1 0 0 ... 0 1 ... 1 0 C15 C7 0 0 ... 1 0 ... 1 0 C14 C6 0 0 ... 1 0 ... 1 0 C13 C5 0 1 ... 1 0 ... 1 0 C12 C4 0 0 ... 1 0 ... 1 0 0 ... 1 0 ... 1 0 1 ... 1 0 ... 1 Gain A = 0 Gain A = +1 ... Gain A = +7 Gain A = -8 ... Gain A = -1 Gain B = 0 Gain B = +1 ... Gain B = +7 Gain B = -8 ... Gain B = -1 CGMS C19 to C16 CGMS C15 to C8 CGMS C7 to C0 0x00 Bit Number 4 3 x x x x x x 0 0 2 x x x 0 1 x x x 0 0 x x x 0 Register Setting Y level value Cr level value Cb level value Disabled Enabled Reset Value 0xA0 0x80 0x80 0x00 0x40 ED/HD Sharpness Filter Gain ED/HD Sharpness Filter Gain, Value B. 0x41 0x42 0x43 1 ED/HD CGMS Data 0 ED/HD CGMS Data 1 ED/HD CGMS Data 2 ED/HD CGMS Data Bits. ED/HD CGMS Data Bits. ED/HD CGMS Data Bits. C19 C11 C3 C18 C10 C2 C17 C9 C1 C16 C8 C0 0x00 0x00 0x00 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1). Table 22. Register 0x44 to Register 0x57 SR7 to SR0 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 Register ED/HD Gamma A0 ED/HD Gamma A1 ED/HD Gamma A2 ED/HD Gamma A3 ED/HD Gamma A4 ED/HD Gamma A5 ED/HD Gamma A6 ED/HD Gamma A7 ED/HD Gamma A8 ED/HD Gamma A9 ED/HD Gamma B0 ED/HD Gamma B1 ED/HD Gamma B2 ED/HD Gamma B3 ED/HD Gamma B4 ED/HD Gamma B5 ED/HD Gamma B6 ED/HD Gamma B7 ED/HD Gamma B8 ED/HD Gamma B9 Bit Description ED/HD Gamma Curve A (Point 24). ED/HD Gamma Curve A (Point 32). ED/HD Gamma Curve A (Point 48). ED/HD Gamma Curve A (Point 64). ED/HD Gamma Curve A (Point 80). ED/HD Gamma Curve A (Point 96). ED/HD Gamma Curve A (Point 128). ED/HD Gamma Curve A (Point 160). ED/HD Gamma Curve A (Point 192). ED/HD Gamma Curve A (Point 224). ED/HD Gamma Curve B (Point 24). ED/HD Gamma Curve B (Point 32). ED/HD Gamma Curve B (Point 48). ED/HD Gamma Curve B (Point 64). ED/HD Gamma Curve B (Point 80). ED/HD Gamma Curve B (Point 96). ED/HD Gamma Curve B (Point 128). ED/HD Gamma Curve B (Point 160). ED/HD Gamma Curve B (Point 192). ED/HD Gamma Curve B (Point 224). Rev. 0 | Page 34 of 88 7 x x x x x x x x x x x x x x x x x x x x 6 x x x x x x x x x x x x x x x x x x x x 5 x x x x x x x x x x x x x x x x x x x x Bit Number 4 3 2 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x x x x Register Setting A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ADV7344 Table 23. Register 0x58 to Register 0x5D SR7 to SR0 0x58 Register ED/HD Adaptive Filter Gain 1 Bit Description ED/HD Adaptive Filter Gain 1, Value A. 7 6 5 Bit Number 4 3 0 0 ... 0 1 ... 1 0 1 ... 1 0 ... 1 0 0 ... 0 1 ... 1 0 1 ... 1 0 ... 1 0 0 ... 0 1 ... 1 0 1 ... 1 0 ... 1 x x x x x x 2 0 0 ... 1 0 ... 1 1 0 0 ... 1 0 ... 1 0 0 1 ... 1 0 ... 1 Register Setting Gain A = 0 Gain A = +1 ... Gain A = +7 Gain A = -8 ... Gain A = -1 Gain B = 0 Gain B = +1 ... Gain B = +7 Gain B = -8 ... Gain B = -1 Gain A = 0 Gain A = +1 ... Gain A = +7 Gain A = -8 ... Gain A = -1 Gain B = 0 Gain B = +1 ... Gain B = +7 Gain B = -8 ... Gain B = -1 Gain A = 0 Gain A = +1 ... Gain A = +7 Gain A = -8 ... Gain A = -1 Gain B = 0 Gain B = +1 ... Gain B = +7 Gain B = -8 ... Gain B = -1 Threshold A Threshold B Threshold C Reset Value 0x00 ED/HD Adaptive Filter Gain 1, Value B. 0 0 ... 0 1 ... 1 0 0 ... 1 0 ... 1 0 0 ... 1 0 ... 1 0x59 ED/HD Adaptive Filter Gain 2 ED/HD Adaptive Filter Gain 2, Value A. 0 0 ... 1 0 ... 1 0 0 ... 1 0 ... 1 0 1 ... 1 0 ... 1 0x00 ED/HD Adaptive Filter Gain 2, Value B. 0 0 ... 0 1 ... 1 0 0 ... 1 0 ... 1 0 0 ... 1 0 ... 1 0x5A ED/HD Adaptive Filter Gain 3 ED/HD Adaptive Filter Gain 3, Value A. 0 0 ... 1 0 ... 1 0 0 ... 1 0 ... 1 0 1 ... 1 0 ... 1 0x00 ED/HD Adaptive Filter Gain 3, Value B. 0x5B 0x5C 0x5D ED/HD Adaptive Filter Threshold A ED/HD Adaptive Filter Threshold B ED/HD Adaptive Filter Threshold C ED/HD Adaptive Filter Threshold A. ED/HD Adaptive Filter Threshold B. ED/HD Adaptive Filter Threshold C. 0 0 ... 0 1 ... 1 x x x 0 0 ... 1 0 ... 1 x x x 0 0 ... 1 0 ... 1 x x x x x x x x x x x x 0x00 0x00 0x00 Rev. 0 | Page 35 of 88 ADV7344 Table 24. Register 0x5E to Register 0x6E SR7 to SR0 0x5E Register ED/HD CGMS Type B Register 0 Bit Description ED/HD CGMS Type B Enable. ED/HD CGMS Type B CRC Enable. ED/HD CGMS Type B Header Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. H5 P7 P15 P23 P31 P39 P47 P55 P63 P71 P79 P87 P95 P103 P111 P119 P127 H4 P6 P14 P22 P30 P38 P46 P54 P62 P70 P78 P86 P94 P102 P110 P118 P126 H3 P5 P13 P21 P29 P37 P45 P53 P61 P69 P77 P85 P93 P101 P109 P117 P125 H2 P4 P12 P20 P28 P36 P44 P52 P60 P68 P76 P84 P92 P100 P108 P116 P124 H1 P3 P11 P19 P27 P35 P43 P51 P59 P67 P75 P83 P91 P99 P107 P115 P123 H0 P2 P10 P18 P26 P34 P42 P50 P58 P66 P74 P82 P90 P98 P106 P114 P122 P1 P9 P17 P25 P33 P41 P49 P57 P65 P73 P81 P89 P97 P105 P113 P121 P0 P8 P16 P24 P32 P40 P48 P56 P64 P72 P80 P88 P96 P104 P112 P120 7 6 5 Bit Number 4 3 2 1 0 0 1 Register Setting Disabled Enabled Disabled Enabled H5 to H0 P7 to P0 P15 to P8 P23 to P16 P31 to P24 P39 to P32 P47 to P40 P55 to P48 P63 to P56 P71 to P64 P79 to P72 P87 to P80 P95 to P88 P103 to P96 P111 to P104 P119 to P112 P127 to P120 Reset Value 0x00 0 1 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E ED/HD CGMS Type B Register 1 ED/HD CGMS Type B Register 2 ED/HD CGMS Type B Register 3 ED/HD CGMS Type B Register 4 ED/HD CGMS Type B Register 5 ED/HD CGMS Type B Register 6 ED/HD CGMS Type B Register 7 ED/HD CGMS Type B Register 8 ED/HD CGMS Type B Register 9 ED/HD CGMS Type B Register 10 ED/HD CGMS Type B Register 11 ED/HD CGMS Type B Register 12 ED/HD CGMS Type B Register 13 ED/HD CGMS Type B Register 14 ED/HD CGMS Type B Register 15 ED/HD CGMS Type B Register 16 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Rev. 0 | Page 36 of 88 ADV7344 Table 25. Register 0x80 to Register 0x83 SR7 to SR0 0x80 Register SD Mode Register 1 Bit Description SD Standard. 7 6 Bit Number 5432 1 0 0 1 1 0 0 1 0 1 Register Setting NTSC. PAL B/D/G/H/I. PAL M. PAL N. LPF NTSC. LPF PAL. Notch NTSC. Notch PAL. SSAF luma. Luma CIF. Luma QCIF. Reserved. 1.3 MHz. 0.65 MHz. 1.0 MHz. 2.0 MHz. Reserved. Chroma CIF. Chroma QCIF. 3.0 MHz. Disabled. Enabled. Refer to Table 32 in the Output Configuration section. Refer to Table 32 in the Output Configuration section. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. No pedestal on YPrPb. 7.5 IRE pedestal on YPrPb. Y = 700 mV/300 mV. Y = 714 mV/286 mV. 700 mV p-p (PAL), 1000 mV p-p (NTSC). 700 mV p-p. 1000 mV p-p. 648 mV p-p. Disabled. Enabled. Closed captioning disabled. Closed captioning on odd field only. Closed captioning on even field only. Closed captioning on both fields. Reserved. Reset Value 0x10 SD Luma Filter. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SD Chroma Filter. 0x82 SD Mode Register 2 SD PrPb SSAF. SD DAC Output 1. SD DAC Output 2. SD Pedestal. SD Square Pixel Mode. SD VCR FF/RW Sync. SD Pixel Data Valid. SD Active Video Edge Control. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0x0B 0x83 SD Mode Register 3 SD Pedestal on YPrPb Output. SD Output Levels Y. SD Output Levels PrPb. 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0x04 SD VBI Open. SD Closed Captioning Field Control. Reserved. Rev. 0 | Page 37 of 88 ADV7344 Table 26. Register 0x84 to Register 0x89 SR7 to SR0 0x84 Register SD Mode Register 4 Bit Description SD VSYNC-3H. 7 6 Bit Number 5432 1 0 0 1 Register Setting Disabled. VSYNC = 2.5 lines (PAL), VSYNC = 3 lines (NTSC). Disabled. Subcarrier phase reset mode enabled. Timing reset mode enabled. SFL mode enabled. 720 pixels. 710 (NTSC), 702 (PAL). Chroma enabled. Chroma disabled. Enabled. Disabled. Disabled. Enabled. DAC 2 = luma, DAC 3 = chroma. DAC 2 = chroma, DAC 3 = luma. 5.17 s. 5.31 s. 5.59 s (must be set for Macrovision compliance). Reserved. Disabled. Enabled. Update field/line counter. Field/line counter free running. Normal. Color reversal enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. 0 must be written to this bit. SD YCrCb input. SD RGB input. Reset Value 0x00 SD SFL/SCR/TR Mode Select. 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SD Active Video Length. SD Chroma. SD Burst. SD Color Bars. SD Luma/Chroma Swap. 0x86 SD Mode Register 5 NTSC Color Subcarrier Adjust (Delay from the falling edge of output HSYNC pulse to start of color burst). 0 0 1 1 0 1 0 1 0x02 Reserved. SD EIA/CEA-861B Synchronization Compliance. Reserved. SD Horizontal/Vertical Counter Mode. 1 SD RGB Color Swap. 0x87 SD Mode Register 6 SD PrPb Scale. SD Y Scale. SD Hue Adjust. SD Brightness. SD Luma SSAF Gain. SD Input Standard Auto Detect. Reserved. SD RGB Input Enable. 0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0x00 Rev. 0 | Page 38 of 88 ADV7344 SR7 to SR0 0x88 Register SD Mode Register 7 Bit Description Reserved. SD Noninterlaced Mode. SD Double Buffering. SD Input Format. 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 7 6 Bit Number 5432 1 0 1 0 1 0 0 Register Setting Disabled. Enabled. Disabled. Enabled. 8-bit input. 16-bit input. 10-bit input. 20-bit input. Disabled. Enabled. Disabled. Enabled. Gamma Correction Curve A. Gamma Correction Curve B. Disabled. -11 IRE. -6 IRE. -1.5 IRE. 0 must be written to this bit. Disabled. Enabled. Disabled. 4 clock cycles. 8 clock cycles. Reserved. 0 must be written to these bits. Reset Value 0x00 SD Digital Noise Reduction. SD Gamma Correction Enable. SD Gamma Correction Curve Select. 0x89 SD Mode Register 8 SD Undershoot Limiter. 0x00 Reserved. SD Black Burst Output on DAC Luma. SD Chroma Delay. Reserved. 1 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. Rev. 0 | Page 39 of 88 ADV7344 Table 27. Register 0x8A to Register 0x98 SR7 to SR0 0x8A Register SD Timing Register 0 Bit Description SD Slave/Master Mode. SD Timing Mode. 7 6 5 Bit Number 4 3 2 1 0 0 1 Register Setting Slave mode. Master mode. Mode 0. Mode 1. Mode 2. Mode 3. No delay. 2 clock cycles. 4 clock cycles. 6 clock cycles. -40 IRE. -7.5 IRE. A low-high-low transition resets the internal SD timing counters. ta = 1 clock cycle. ta = 4 clock cycles. ta = 16 clock cycles. ta = 128 clock cycles. tb = 0 clock cycles. tb = 4 clock cycles. tb = 8 clock cycles. tb = 18 clock cycles. tc = tb. tc = tb + 32 s. 1 clock cycle. 4 clock cycles. 16 clock cycles. 128 clock cycles. 0 clock cycles. 1 clock cycle. 2 clock cycles. 3 clock cycles. Subcarrier Frequency Bits[7:0]. Subcarrier Frequency Bits[15:8]. Subcarrier Frequency Bits[23:16]. Subcarrier Frequency Bits[31:24]. Subcarrier Phase Bits[9:2]. Extended Data Bits[7:0]. Extended Data Bits[15:8]. Data Bits[7:0]. Data Bits[15:8]. Setting any of these bits to 1 disables pedestal on the line number indicated by the bit settings. Reset Value 0x08 0 0 1 1 1 0 0 1 1 0 1 x 0 1 0 1 0 1 0 1 Reserved. SD Luma Delay. SD Minimum Luma Value. SD Timing Reset. 0x8B SD Timing Register 1 (Note: Applicable in master modes only, that is, Subaddress 0x8A, Bit 0 = 1.) SD HSYNC Width. 0 0 1 1 0 0 1 1 x x 0 0 1 1 0 0 1 1 x x x x x x x x x 17 25 17 25 0 1 0 1 x x x x x x x x x 16 24 16 24 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0x00 SD HSYNC to VSYNC Delay. SD HSYNC to VSYNC Rising Edge Delay (Mode 1 Only). VSYNC Width (Mode 2 Only). HSYNC to Pixel Data Adjust. 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 1 SD FSC Register 0 1 SD FSC Register 11 SD FSC Register 21 SD FSC Register 31 SD FSC Phase SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Pedestal Register 0 SD Pedestal Register 1 SD Pedestal Register 2 SD Pedestal Register 3 Subcarrier Frequency Bits[7:0]. Subcarrier Frequency Bits[15:8]. Subcarrier Frequency Bits[23:16]. Subcarrier Frequency Bits[31:24]. Subcarrier Phase Bits[9:2]. Extended Data on Even Fields. Extended Data on Even Fields. Data on Odd Fields. Data on Odd Fields. Pedestal on Odd Fields. Pedestal on Odd Fields. Pedestal on Even Fields. Pedestal on Even Fields. x x x x x x x x x 15 23 15 23 x x x x x x x x x 14 22 14 22 x x x x x x x x x 13 21 13 21 x x x x x x x x x 12 20 12 20 x x x x x x x x x 11 19 11 19 x x x x x x x x x 10 18 10 18 0x1F 0x7C 0xF0 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 SD subcarrier frequency registers default to NTSC subcarrier frequency values. Rev. 0 | Page 40 of 88 ADV7344 Table 28. Register 0x99 to Register 0xA5 SR7 to SR0 0x99 Register SD CGMS/WSS 0 Bit Description SD CGMS Data. SD CGMS CRC. SD CGMS on Odd Fields. SD CGMS on Even Fields. SD WSS. 0x9A SD CGMS/WSS 1 SD CGMS/WSS Data. SD CGMS Data. SD CGMS/WSS Data. LSBs for SD Y Scale Value. LSBs for SD Cb Scale Value. LSBs for SD Cr Scale Value. LSBs for SD FSC Phase. SD Y Scale Value. SD Cb Scale Value. SD Cr Scale Value. SD Hue Adjust Value. SD Brightness Value. SD Blank WSS Data. SD Luma SSAF Gain/Attenuation. Note: Only applicable if Register 0x87, Bit 4 = 1. x x x x 0 1 x x x x x x 0 1 7 6 5 Bit Number 4 3 2 x x 0 1 1 x 0 x Register Setting CGMS Data Bits[C19:C16] Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled CGMS Data Bits[C13:C8] or WSS Data Bits[W13:W8] CGMS Data Bits[C15:C14] CGMS Data Bits[C7:C0] or WSS Data Bits[W7:W0] SD Y Scale Bits[1:0] SD Cb Scale Bits[1:0] SD Cr Scale Bits[1:0] Subcarrier Phase Bits[1:0] SD Y Scale Bits[7:2] SD Cb Scale Bits[7:2] SD Cr Scale Bits[7:2] SD Hue Adjust Bits[7:0] SD Brightness Bits[6:0] Disabled Enabled -4 dB ... 0 dB ... +4 dB Reset Value 0x00 0 1 0x00 0x9B 0x9C SD CGMS/WSS 2 SD Scale LSB Register x x x x x x x x 0x00 0x00 x x x x x x x 0 1 0 ... 0 ... 1 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x 0x9D 0x9E 0x9F 0xA0 0xA1 SD Y Scale Register SD Cb Scale Register SD Cr Scale Register SD Hue Register SD Brightness/WSS x x x x x x x x x x x x x x x 0x00 0x00 0x00 0x00 0x00 0xA2 SD Luma SSAF 0 ... 1 ... 1 0 ... 1 ... 0 0 ... 0 ... 0 0x00 Reserved. Rev. 0 | Page 41 of 88 ADV7344 SR7 to SR0 0xA3 Register SD DNR 0 Bit Description Coring Gain Border. Note: In DNR mode, the values in brackets apply. 7 6 5 Bit Number 4 3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 ...... 1 1 1 1 2 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 Register Setting No gain +1/16 [-1/8] +2/16 [-2/8] +3/16 [-3/8] +4/16 [-4/8] +5/16 [-5/8] +6/16 [-6/8] +7/16 [-7/8] +8/16 [-1] No gain. +1/16 [-1/8] +2/16 [-2/8] +3/16 [-3/8] +4/16 [-4/8] +5/16 [-5/8] +6/16 [-6/8] +7/16 [-7/8] +8/16 [-1] 0 1 ... 62 63 2 pixels 4 pixels 8 pixels 16 pixels Filter A Filter B Filter C Filter D DNR mode DNR sharpness mode 0 pixel offset 1 pixel offset ... 14 pixel offset 15 pixel offset Reset Value 0x00 Coring Gain Data. Note: In DNR mode, the values in brackets apply. 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0xA4 SD DNR 1 DNR Threshold. 0 0 1 1 0 0 1 1 0 0 0 ... 1 1 0 0 ... 1 1 0 0 ... 1 1 0 1 ... 0 1 0x00 Border Area. Block Size Control. 0xA5 SD DNR 2 DNR Input Select. 0 1 0 1 0 0 0 1 0 1 0 1 ... 0 1 0 1 1 0 1 0 1 0 0x00 DNR Mode. DNR Block Offset. 0 0 ... 1 1 0 0 ... 1 1 0 0 ... 1 1 Rev. 0 | Page 42 of 88 ADV7344 Table 29. Register 0xA6 to Register 0xBB SR7 to SR0 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB Register SD Gamma A0 SD Gamma A1 SD Gamma A2 SD Gamma A3 SD Gamma A4 SD Gamma A5 SD Gamma A6 SD Gamma A7 SD Gamma A8 SD Gamma A9 SD Gamma B0 SD Gamma B1 SD Gamma B2 SD Gamma B3 SD Gamma B4 SD Gamma B5 SD Gamma B6 SD Gamma B7 SD Gamma B8 SD Gamma B9 SD Brightness Detect Field Count Register Bit Description SD Gamma Curve A (Point 24). SD Gamma Curve A (Point 32). SD Gamma Curve A (Point 48). SD Gamma Curve A (Point 64). SD Gamma Curve A (Point 80). SD Gamma Curve A (Point 96). SD Gamma Curve A (Point 128). SD Gamma Curve A (Point 160). SD Gamma Curve A (Point 192). SD Gamma Curve A (Point 224). SD Gamma Curve B (Point 24). SD Gamma Curve B (Point 32). SD Gamma Curve B (Point 48). SD Gamma Curve B (Point 64). SD Gamma Curve B (Point 80). SD Gamma Curve B (Point 96). SD Gamma Curve B (Point 128). SD Gamma Curve B (Point 160). SD Gamma Curve B (Point 192). SD Gamma Curve B (Point 224). SD Brightness Value. Field Count. Reserved. Revision Code. 7 x x x x x x x x x x x x x x x x x x x x x 6 x x x x x x x x x x x x x x x x x x x x x 5 x x x x x x x x x x x x x x x x x x x x x Bit Number 432 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 000 1 x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x x x x x x Register Setting A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Read only. Read only. Reserved. Read only. Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xXX 0x0X 0 0 Table 30. Register 0xE0 to Register 0xF1 SR7 to SR0 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 Register Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Bit Description MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bit. 7 x x x x x x x x x x x x x x x x x 0 6 x x x x x x x x x x x x x x x x x 0 Bit Number 5 4 3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 2 x x x x x x x x x x x x x x x x x 0 1 x x x x x x x x x x x x x x x x x 0 0 x x x x x x x x x x x x x x x x x x Register Setting Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Bits[7:1] must be 0. Rev. 0 | Page 43 of 88 ADV7344 INPUT CONFIGURATION The ADV7344 supports a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7344 defaults to standard definition only (SD only) upon power-up. Table 31 provides an overview of all possible input configurations. Each input mode is described in detail in the following sections. In 16-/20-bit 4:2:2 YCrCb input mode, the Y pixel data is input on Pin S9 to Pin S2/S0 (or Pin Y9 to Pin Y2/Y0, depending on Subaddress 0x01, Bit 7), with S0/Y0 being the LSB in 20-bit input mode. The CrCb pixel data is input on Pin Y9 to Pin Y2/Y0 (or Pin C9 to Pin C2/C0, depending on Subaddress 0x01, Bit 7), with Y0/C0 being the LSB in 20-bit input mode. STANDARD DEFINITION ONLY Subaddress 0x01, Bits[6:4] = 000 Standard definition (SD) YCrCb data can be input in 4:2:2 format. Standard definition (SD) RGB data can be input in 4:4:4 format. A 27 MHz clock signal must be provided on the CLKIN_A pin. Input synchronization signals are provided on the S_HSYNC and S_VSYNC pins. 24-/30-Bit 4:4:4 RGB Mode Subaddress 0x87, Bit 7 = 1 In 24-/30-bit 4:4:4 RGB input mode, the red pixel data is input on Pin S9 to Pin S2/S0, the green pixel data is input on Pin Y9 to Pin Y2/Y0, and the blue pixel data is input on Pin C9 to Pin C2/C0. S0, Y0, and C0 are the respective bus LSBs in 30-bit input mode. ADV7344 2 MPEG2 DECODER 27MHz S_VSYNC, S_HSYNC 8-/10-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 0 In 8-/10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is input on Pin S9 to Pin S2/S0 (or Pin Y9 to Pin Y2/Y0, depending on Subaddress 0x01, Bit 7), with S0/Y0 being the LSB in 10-bit input mode. ITU-R BT.601/656 input standard is supported. CLKIN_A YCrCb 10 S[9:0] OR Y[9:0] 1 06400-051 16-/20-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1 Table31. Input Configuration S Input Mode1 000 SD Only 8-/10-Bit YCrCb2, 3 16-/20-Bit YCrCb2, 3, 4 8-/10-Bit YCrCb2, 3 16-/20-Bit YCrCb2, 3, 4 24-/30-Bit RGB4 ED/HD-SDR Only3, 5, 6, 7 16-/20-Bit YCrCb 24-/30-Bit YCrCb 24-/30-Bit RGB4 ED/HD-DDR Only (8-/10-Bit) 3, 6, 7 SD, ED/HD-SDR (24-/30-Bit)3, 6, 7, 8 SD, ED/HD-DDR (16-/20-Bit)3, 6, 7, 8 ED Only (54 MHz) (8-/10-Bit)3, 6, 7 R 9 8 7 6 5 4 3 2 1 0 9 8 Y NOTES 1SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 51. SD Only Example Application C 1 0 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 Y/C/S Bus Swap (0x01[7]) = 0 YCrCb Y 001 Cr R 010 011 100 111 CrCb Y/C/S Bus Swap (0x01[7]) = 1 YCrCb Y SD RGB Input Enable (0x87[7]) = 1 G ED/HD RGB Input Enable (0x35[1]) = 0 Y Y ED/HD RGB Input Enable (0x35[1]) = 1 G YCrCb Y (ED/HD) YCrCb (ED/HD) YCrCb CrCb B CrCb Cb B YCrCb (SD) YCrCb (SD) CrCb (ED/HD) 1 2 The input mode is determined by Subaddress 0x01, Bits[6:4]. In SD only (YCrCb) mode, the format of the input data is determined by Subaddress 0x88, Bits[4:3]. See Table 26 for more information. 3 For 8-/16-/24-bit inputs, only the eight most significant bits (MSBs) of each applicable input bus are used 4 External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported. 5 In ED/HD-SDR only (YCrCb) mode, the format of the input data is determined by Subaddress 0x33, Bit 6. See Table 19 for more information. 6 ED = enhanced definition = 525p and 625p. 7 The bus width of the ED/HD input data is determined by Subaddress 0x33, Bit 2 (0 = 8-bit, 1 = 10-bit). See Table 19 for more information. 8 The bus width of the SD input data is determined by Subaddress 0x88, Bit 4 (0 = 8-bit, 1 = 10-bit). See Table 26 for more information. Rev. 0 | Page 44 of 88 ADV7344 ENHANCED DEFINITION/HIGH DEFINITION ONLY Subaddress 0x01, Bits[6:4] = 001 or 010 Enhanced definition (ED) or high definition (HD) YCrCb data can be input in either 4:2:2 or 4:4:4 formats. If desired, dual data rate (DDR) pixel data inputs can be employed (4:2:2 format only). Enhanced definition (ED) or high definition (HD) RGB data can be input in 4:4:4 format (single data rate only). The clock signal must be provided on the CLKIN_A pin. Input synchronization signals are provided on the P_HSYNC, P_VSYNC and P_BLANK pins. 24-/30-Bit 4:4:4 RGB Mode Subaddress 0x35, Bit 1 = 1 In 24-/30-bit 4:4:4 RGB input mode, the red pixel data is input on Pin S9 to Pin S2/S0, the green pixel data is input on Pin Y9 to Pin Y2/Y0, and the blue pixel data is input on Pin C9 to Pin C2/C0. S0, Y0, and C0 are the respective bus LSBs in 30-bit input mode. MPEG2 DECODER YCrCb Cb 10 Cr 10 INTERLACED TO PROGRESSIVE Y 10 3 ADV7344 CLKIN_A C[9:0] S[9:0] Y[9:0] 06400-054 16-/20-Bit 4:2:2 YCrCb Mode (SDR) Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1 In 16-/20-bit 4:2:2 YCrCb input mode, the Y pixel data is input on Pin Y9 to Pin Y2/Y0, with Y0 being the LSB in 20-bit input mode. The CrCb pixel data is input on Pin C9 to Pin C2/C0, with C0 being the LSB in 20-bit input mode. P_VSYNC, P_HSYNC, P_BLANK Figure 54. ED/HD Only Example Application 8-/10-Bit 4:2:2 YCrCb Mode (DDR) Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1 In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input on Pin Y9 to Pin Y2/Y0 upon either the rising or falling edge of CLKIN_A. Y0 is the LSB in 10-bit input mode. The CrCb pixel data is also input on Pin Y9 to Pin Y2/Y0 upon the opposite edge of CLKIN_A. Y0 is the LSB in 10-bit input mode. Whether the Y data is clocked in upon the rising or falling edge of CLKIN_A is determined by Subaddress 0x01, Bits[2:1] (see Figure 52 and Figure 53). CLKIN_A SIMULTANEOUS STANDARD DEFINITION AND ENHANCED DEFINITION/HIGH DEFINITION Subaddress 0x01, Bits[6:4] = 011 or 100 The ADV7344 is able to simultaneously process SD 4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27 MHz SD clock signal must be provided on the CLKIN_A pin. The ED/HD clock signal must be provided on the CLKIN_B pin. SD input synchronization signals are provided on the S_HSYNC and S_VSYNC pins. ED/HD input synchronization signals are provided on the P_HSYNC, P_VSYNC and P_BLANK pins. SD 8-/10-Bit 4:2:2 YCrCb and ED/HD-SDR 16-/20-Bit 4:2:2 YCrCb The SD 8-/10-bit 4:2:2 YCrCb pixel data is input on Pin S9 to Pin S2/S0, with S0 being the LSB in 10-bit input mode. Y[9:0] 3FF 00 00 XY Cb0 Y0 Cr0 Y1 06400-052 NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE. The ED/HD 16-/20-bit 4:2:2 Y pixel data is input on Pin Y9 to Pin Y2/Y0, with Y0 being the LSB in 20-bit input mode. The ED/HD 16-/20-bit 4:2:2 CrCb pixel data is input on Pin C9 to Pin C2/C0, with C0 being the LSB in 20-bit input mode. Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)--Option A CLKIN_A SD 8-/10-Bit 4:2:2 YCrCb and ED/HD-DDR 8-/10-Bit 4:2:2 YCrCb 3FF 00 00 XY Y0 Cb0 Y1 Cr0 06400-053 Y[9:0] NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE. The SD 8-/10-bit 4:2:2 YCrCb pixel data is input on Pin S9 to Pin S2/S0, with S0 being the LSB in 10-bit input mode. The ED/HD-DDR 8-/10-bit 4:2:2 Y pixel data is input on Pin Y9 to Pin Y2/Y0 upon the rising or falling edge of CLKIN_B. Y0 is the LSB in 10-bit input mode. The ED/HD-DDR 8-/10-bit 4:2:2 CrCb pixel data is also input on Pin Y9 to Pin Y2/Y0 upon the opposite edge of CLKIN_B. Y0 is the LSB in 10-bit input mode. Whether the ED/HD Y data is clocked in upon the rising or falling edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1] (See the input sequence shown in Figure 52 and Figure 53). Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)--Option B 24-/30-Bit 4:4:4 YCrCb Mode Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0 In 24-/30-bit 4:4:4 YCrCb input mode, the Y pixel data is input on Pin Y9 to Pin Y2/Y0, with Y0 being the LSB in 30-bit input mode. The Cr pixel data is input on Pin S9 to Pin S2/S0, with S0 being the LSB in 30-bit input mode. The Cb pixel data is input on Pin C9 to Pin C2/C0, with C0 being the LSB in 30-bit input mode. Rev. 0 | Page 45 of 88 ADV7344 Whether the ED/HD Y data is clocked in upon the rising or falling edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1] (See the input sequence shown in Figure 52 and Figure 53). ADV7344 CrCb SD DECODER 27MHz YCrCb 10 ED DECODER 525p OR 625p 2 S_VSYNC, S_HSYNC CLKIN_A S[9:0] ENHANCED DEFINITION ONLY (AT 54 MHz) Subaddress 0x01, Bits[6:4] = 111 Enhanced definition (ED) YCrCb data can be input in an interleaved 4:2:2 format on an 8-/10-bit bus at a rate of 54 MHz. A 54 MHz clock signal must be provided on the CLKIN_A pin. Input synchronization signals are provided on the P_HSYNC, P_VSYNC, and P_BLANK pins. The interleaved pixel data is input on Pin Y9 to Pin Y2/Y0, with Y0 being the LSB in 10-bit input mode. CLKIN_A 06400-057 CrCb 10 Y 10 3 27MHz C[9:0] Y[9:0] P_VSYNC, P_HSYNC, P_BLANK CLKIN_B 06400-055 Y[9:0] 3FF 00 00 XY Cb0 Y0 Cr0 Y1 Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV) Figure 55. Simultaneous SD and ED Example Application ADV7344 2 SD DECODER 27MHz YCrCb 10 HD DECODER 1080i OR 720p OR 1035i S_VSYNC, S_HSYNC CLKIN_A S[9:0] MPEG2 DECODER YCrCb 54MHz CLKIN_A ADV7344 YCrCb 10 INTERLACED TO PROGRESSIVE 3 Y[9:0] 06400-058 CrCb 10 Y 10 3 74.25MHz C[9:0] Y[9:0] P_VSYNC, P_HSYNC, P_BLANK CLKIN_B P_VSYNC, P_HSYNC, P_BLANK Figure 58. ED Only (at 54 MHz) Example Application 06400-056 Figure 56. Simultaneous SD and HD Example Application Rev. 0 | Page 46 of 88 ADV7344 OUTPUT CONFIGURATION The ADV7344 supports a number of different output configurations. Table 32 to Table 35 lists all possible output configurations. Table 32. SD Only Output Configurations RGB/YPrPb Output Select 1 (0x02, Bit 5) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 SD DAC Output 2 (0x82, Bit 2) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SD DAC Output 1 (0x82, Bit 1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SD Luma/Chroma Swap (0x84, Bit 7) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC 1 G G CVBS CVBS CVBS CVBS G G Y Y CVBS CVBS CVBS CVBS Y Y DAC 2 B B Luma Chroma B B Luma Chroma Pb Pb Luma Chroma Pb Pb Luma Chroma DAC 3 R R Chroma Luma R R Chroma Luma Pr Pr Chroma Luma Pr Pr Chroma Luma DAC 4 CVBS CVBS G G G G CVBS CVBS CVBS CVBS Y Y Y Y CVBS CVBS DAC 5 Luma Chroma B B Luma Chroma B B Luma Chroma Pb Pb Luma Chroma Pb Pb DAC 6 Chroma Luma R R Chroma Luma R R Chroma Luma Pr Pr Chroma Luma Pr Pr If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7. Table 33. ED/HD Only Output Configurations RGB/YPrPb Output Select (0x02, Bit 5) 0 0 1 1 ED/HD Color DAC Swap (0x35, Bit 3) 0 1 0 1 DAC 1 G G Y Y DAC 2 B R Pb Pr DAC 3 R B Pr Pb DAC 4 N/A N/A N/A N/A DAC 5 N/A N/A N/A N/A DAC 6 N/A N/A N/A N/A Table 34. Simultaneous SD and ED/HD Output Configurations RGB/YPrPb Output Select (0x02, Bit 5) 0 0 0 0 1 1 1 1 ED/HD Color DAC Swap (0x35, Bit 3) 0 0 1 1 0 0 1 1 SD Luma/Chroma Swap (0x84, Bit 7) 0 1 0 1 0 1 0 1 DAC 1 (ED/HD) G G G G Y Y Y Y DAC 2 (ED/HD) B B R R Pb Pb Pr Pr DAC 3 (ED/HD) R R B B Pr Pr Pb Pb DAC 4 (SD) CVBS CVBS CVBS CVBS CVBS CVBS CVBS CVBS DAC 5 (SD) Luma Chroma Luma Chroma Luma Chroma Luma Chroma DAC 6 (SD) Chroma Luma Chroma Luma Chroma Luma Chroma Luma Table 35. ED Only (at 54 MHz) Output Configurations RGB/YPrPb Output Select (0x02, Bit 5) 0 0 1 1 ED/HD Color DAC Swap (0x35, Bit 3) 0 1 0 1 Rev. 0 | Page 47 of 88 DAC 1 G G Y Y DAC 2 B R Pb Pr DAC 3 R B Pr Pb DAC 4 N/A N/A N/A N/A DAC 5 N/A N/A N/A N/A DAC 6 N/A N/A N/A N/A ADV7344 FEATURES OUTPUT OVERSAMPLING The ADV7344 includes two on-chip phase locked loops (PLLs) that allow for oversampling of SD, ED, and HD video data. Table 36 shows the various oversampling rates supported in the ADV7344. A clock signal must be provided on the CLKIN_A pin. P_HSYNC and P_VSYNC must be toggled by the user to generate the appropriate horizontal and vertical synchronization pulses on the analog output from the encoder. Figure 59 illustrates the various output levels that can be generated. Table 37 lists the transitions required to generate these output levels. Embedded EAV/SAV timing codes are not supported in ED/HD nonstandard timing mode. The user must ensure that appropriate pixel data is applied to the encoder where the blanking level is expected at the output. Macrovision and output oversampling are not available in ED/HD nonstandard timing mode. ANALOG OUTPUT a b c 06400-141 SD Only, ED Only, and HD Only Modes PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is unused in these modes. PLL 1 is disabled by default and can be enabled using Subaddress 0x00, Bit 1 = 0. SD and ED/HD Simultaneous Modes Both PLL 1 and PLL 2 are used in simultaneous modes. The use of two PLLs allows for independent oversampling of SD and ED/HD video. PLL 1 is used to oversample SD video data, and PLL 2 is used to oversample ED/HD video data. In simultaneous modes, PLL 2 is always enabled. PLL 1 is disabled by default and can be enabled using Subaddress 0x00, Bit 1 = 0. b ACTIVE VIDEO b BLANKING LEVEL ED/HD NONSTANDARD TIMING MODE Subaddress 0x30, Bits[7:3] = 00001 For any ED/HD input data that does not conform to the standards available in the ED/HD input mode table (Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard timing mode can be used to interface to the ADV7344. ED/HD nonstandard timing mode can be enabled by setting Subaddress 0x30, Bits[7:3] to 00001. Table 36. Output Oversampling Modes and Rates Input Mode Subaddress 0x01 [6:4] 000 SD only 000 SD only 001/010 ED only 001/010 ED only 001/010 HD only 001/010 HD only 011/100 SD and ED 011/100 SD and ED 011/100 SD and HD 011/100 SD and HD 111 ED only (at 54 MHz) 111 ED only (at 54 MHz) PLL and Oversampling Control Subaddress 0x00, Bit 1 1 0 1 0 1 0 1 0 1 0 1 0 a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL. b = BLANKING LEVEL/ACTIVE VIDEO LEVEL. c = SYNCHRONIZATION PULSE LEVEL. Figure 59. ED/HD Nonstandard Timing Mode Output Levels Oversampling Mode and Rate SD (2x) SD (16x) ED (1x) ED (8x) HD (1x) HD (4x) SD (2x) and ED (8x) SD (16x) and ED (8x) SD (2x) and HD (4x) SD (16x) and HD (4x) ED only (at 54 MHz) (1x) ED only (at 54 MHz) (8x) Table 37. ED/HD Nonstandard Timing Mode Synchronization Signal Generation Output Level Transition 1 bc ca ab cb 1 2 P_HSYNC 10 0 01 01 P_VSYNC 1 0 or 0 2 01 1 0 a = tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. If P_VSYNC = 1, it should transition to 0. If P_VSYNC = 0, it should remain at 0. If tri-level synchronization pulse generation is not required, P_VSYNC should always be 0. Rev. 0 | Page 48 of 88 ADV7344 ED/HD TIMING RESET Subaddress 0x34, Bit 0 An ED/HD timing reset is achieved by toggling the ED/HD timing reset control bit (Subaddress 0x34, Bit 0) from 0 to 1. In this state, the horizontal and vertical counters remain reset. When this bit is set back to 0, the internal counters resume counting. This timing reset applies to the ED/HD timing counters only. Subcarrier Phase Reset (SCR) Mode In this mode (Subaddress 0x84, Bits[2:1] = 01), a low-to-high transition on the SFL/MISO pin (Pin 48) resets the subcarrier phase to 0 on the field following the subcarrier phase reset. This reset signal must be held high for a minimum of one clock cycle. Because the field counter is not reset, it is recommended that the reset signal be applied in Field 7 (PAL) or Field 3 (NTSC). The reset of the phase then occurs on the next field, that is, Field 1, lined up correctly with the internal counters. The field count register at Subaddress 0xBB can be used to identify the number of the active field. SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER PHASE RESET, AND TIMING RESET Subaddress 0x84, Bits[2:1] Together with the SFL/MISO pin and SD Mode Register 4 (Subaddress 0x84, Bits[2:1]), the ADV7344 can be used in timing reset mode, subcarrier phase reset mode, or SFL mode. Subcarrier Frequency Lock (SFL) Mode In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7344 can be used to lock to an external video source. The SFL mode allows the ADV7344 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device such as an ADV7403 video decoder (see Figure 62) that outputs a digital data stream in the SFL format, the part automatically changes to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67 bits wide, and the subcarrier is contained in Bit 0 to Bit 21. Each bit is two clock cycles long. Timing Reset (TR) Mode In this mode (Subaddress 0x84, Bits[2:1] = 10), a timing reset is achieved in a low-to-high transition on the SFL/MISO pin (Pin 48). In this state, the horizontal and vertical counters remain reset. Upon releasing this pin (set to low), the internal counters resume counting, starting with Field 1, and the subcarrier phase is reset. The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the SD timing counters only. DISPLAY START OF FIELD 4 OR 8 FSC PHASE = FIELD 4 OR 8 307 310 313 320 NO TIMING RESET APPLIED DISPLAY START OF FIELD 1 FSC PHASE = FIELD 1 307 1 2 3 4 5 6 7 21 TIMING RESET PULSE TIMING RESET APPLIED Figure 60. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits[2:1] = 10) DISPLAY START OF FIELD 4 OR 8 FSC PHASE = FIELD 4 OR 8 307 NO FSC RESET APPLIED 310 313 320 DISPLAY START OF FIELD 4 OR 8 FSC PHASE = FIELD 1 307 310 313 320 FSC RESET APPLIED Figure 61. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits[2:1] = 01) Rev. 0 | Page 49 of 88 06400-062 FSC RESET PULSE 06400-061 ADV7344 ADV7344 CLKIN_A LCC1 COMPOSITE VIDEO1 SFL P19 TO P10 4 BITS RESERVED SFL/MISO Y9 TO Y0/ S9 TO S05 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 SEQUENCE BIT3 FSC PLL INCREMENT2 0 RESET BIT4 RESERVED ADV7403 VIDEO DECODER 14 BITS H/L TRANSITION SUBCARRIER COUNT START LOW PHASE 128 13 0 RTC TIME SLOT 01 21 14 19 VALID INVALID SAMPLE SAMPLE 8/LINE LOCKED CLOCK 6768 5 BITS RESERVED 1FOR EXAMPLE, VCR OR CABLE. 2F SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7344 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. 3SEQUENCE BIT 4RESET ADV7344 DDS. 5SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 62. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits[2:1] = 11) SD VCR FF/RW SYNC Subaddress 0x82, Bit 5 In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, that is, in fast forward or rewind modes. In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields is reached. In rewind mode, this sync signal usually occurs after the total number of lines/fields is reached. Conventionally, this means that the output video has corrupted field signals because one signal is generated by the incoming video and another is generated when the internal line/field counters reach the end of a field. When the VCR FF/RW sync control is enabled (Subaddress 0x82, Bit 5), the line/field counters are updated according to the incoming VSYNC signal and when the analog output matches the incoming VSYNC signal. This control is available in all slave-timing modes except Slave Mode 0. In SD Timing Mode 0 (slave option), if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten. It is possible to use VBI in this timing mode as well. If CGMS is enabled and VBI is disabled, the CGMS data is nevertheless available at the output. SD SUBCARRIER FREQUENCY REGISTERS Subaddress 0x8C to Subaddress 0x8F Four 8-bit registers are used to set up the subcarrier frequency. The value of these registers is calculated using: Subcarrier Frequency Register = Number of subcarrier periods in one video line Number of 27 MHz clk cycles in one video line x 2 32 where the sum is rounded to the nearest integer. For example, in NTSC mode: 227.5 32 Subcarrier Register Value = x 2 = 569408543 1716 where: Subcarrier Register Value = 569408543d = 0x21F07C1F SD FSC Register 0: 0x1F SD FSC Register 1: 0x7C SD FSC Register 2: 0xF0 SD FSC Register 3: 0x21 VERTICAL BLANKING INTERVAL Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4 The ADV7344 is able to accept input data that contains VBI data (such as CGMS, WSS, VITS) in SD, ED, and HD modes. If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress 0x83, Bit 4 for SD), VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave timing modes. For the SMPTE 293M (525p) standard, VBI data can be inserted on Line 13 to Line 42 of each frame, or on Line 6 to Line 43 for the ITU-R BT.1358 (625p) standard. VBI data can be present on Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL. Programming the FSC The subcarrier frequency register value is divided into four FSC registers as shown in the previous example. The four subcarrier frequency registers must be updated sequentially, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3. The subcarrier frequency updates only after the last subcarrier frequency register byte has been received by the ADV7344. Rev. 0 | Page 50 of 88 06400-063 PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE ADV7344 Typical FSC Values Table 38 outlines the values that should be written to the subcarrier frequency registers for NTSC and PAL B/D/G/H/I. Table 38. Typical FSC Values Subaddress 0x8C 0x8D 0x8E 0x8F Description FSC0 FSC1 FSC2 FSC3 NTSC 0x1F 0x7C 0xF0 0x21 PAL B/D/G/H/I 0xCB 0x8A 0x09 0x2A A 27 MHz clock signal must be provided on the CLKIN_A pin. Embedded EAV/SAV timing codes or external horizontal and vertical synchronization signals provided on the S_HSYNC and S_VSYNC pins can be used to synchronize the input pixel data. All input configurations, output configurations, and features available in NTSC and PAL modes are available in SD noninterlaced mode. For 240p/59.94 Hz input, the ADV7344 should be configured for NTSC operation, and Subaddress 0x88, Bit 1 should be set to 1. For 288p/50 Hz input, the ADV7344 should be configured for PAL operation and Subaddress 0x88, Bit 1 should be set to 1. SD NONINTERLACED MODE Subaddress 0x88, Bit 1 The ADV7344 supports a SD noninterlaced mode. Using this mode, progressive inputs at twice the frame rate of NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input into the ADV7344. The SD noninterlaced mode can be enabled using Subaddress 0x88, Bit 1. SD SQUARE PIXEL MODE Subaddress 0x82, Bit 4 The ADV7344 can be used to operate in square pixel mode (Subaddress 0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. In square pixel mode, the timing diagrams shown in Figure 63 and Figure 64 apply. ANALOG VIDEO EAV CODE INPUT PIXELS Y C F0 0X818 1 Y r F0 0Y000 0 4 CLOCK 4 CLOCK END OF ACTIVE VIDEO LINE 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 272 CLOCK 344 CLOCK SAV CODE C C 8 1 8 1 F 0 0X CY C YC Y rYb b 0000F00Yb r 4 CLOCK 4 CLOCK START OF ACTIVE VIDEO LINE 06400-064 NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) 1280 CLOCK 1536 CLOCK Figure 63. Square Pixel Mode EAV/SAV Embedded Timing HSYNC FIELD PIXEL DATA Cb Y Cr Y PAL = 308 CLOCK CYCLES NTSC = 236 CLOCK CYCLES Figure 64. Square Pixel Mode Active Pixel Timing Rev. 0 | Page 51 of 88 06400-065 ADV7344 FILTERS Table 39 shows an overview of the programmable filters available on the ADV7344. Table 39. Selectable Filters Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1.3 MHz SD Chroma 2.0 MHz SD Chroma 3.0 MHz SD Chroma CIF SD Chroma QCIF SD PrPb SSAF ED/HD Chroma Input ED/HD Sinc Compensation Filter ED/HD Chroma SSAF Subaddress 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x82 0x33 0x33 0x33 GAIN (dB) 0 -10 EXTENDED (SSAF) PrPb FILTER MODE -20 -30 -40 -50 0 1 2 3 4 FREQUENCY (MHz) 5 6 Figure 65. PrPb SSAF Filter If this filter is disabled, one of the chroma filters shown in Table 40 can be selected and used for the CVBS or luma/chroma signal. Table 40. Internal Filter Specifications Filter Luma LPF NTSC Luma LPF PAL Luma Notch NTSC Luma Notch PAL Luma SSAF Luma CIF Luma QCIF Chroma 0.65 MHz Chroma 1.0 MHz Chroma 1.3 MHz Chroma 2.0 MHz Chroma 3.0 MHz Chroma CIF Chroma QCIF 1 SD Internal Filter Response Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0 The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. The PrPb filter supports several different frequency responses, including six low-pass responses, a CIF response, and a QCIF response, as shown in Figure 39 and Figure 40. If SD SSAF gain is enabled (Subaddress 0x87, Bit 4), there are 13 response options in the -4 dB to +4 dB range. The desired response can be programmed using Subaddress 0xA2. The variation of frequency responses are shown in Figure 36 to Figure 38. In addition to the chroma filters listed in Table 39, the ADV7344 contains an SSAF filter specifically designed for the color difference component outputs, Pr and Pb. This filter has a cutoff frequency of ~2.7 MHz and a gain of -40 dB at 3.8 MHz (see Figure 65). This filter can be controlled with Subaddress 0x82, Bit 0. Pass-Band Ripple (dB)1 0.16 0.1 0.09 0.1 0.04 0.127 Monotonic Monotonic Monotonic 0.09 0.048 Monotonic Monotonic Monotonic 3 dB Bandwidth (MHz)2 4.24 4.81 2.3/4.9/6.6 3.1/5.6/6.4 6.45 3.02 1.5 0.65 1 1.395 2.2 3.2 0.65 0.5 Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the -3 dB points. 2 3 dB bandwidth refers to the -3 dB cutoff frequency. ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3 The ADV7344 includes a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled by default. It can be disabled using Subaddress 0x33, Bit 3. The benefit of the filter is illustrated in Figure 66 and Figure 67. Rev. 0 | Page 52 of 88 06400-066 -60 ADV7344 0.5 0.4 0.3 0.2 GAIN (dB) Table 41. Sample Color Values for EIA 770.2/EIA770.3 ED/HD Output Standard Selection Sample Color White Black Red Green Blue Yellow Cyan Magenta 0 5 10 15 20 FREQUENCY (MHz) 25 30 06400-067 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 Y Value 235 (0xEB) 16 (0x10) 81 (0x51) 145 (0x91) 41 (0x29) 210 (0xD2) 170 (0xAA) 106 (0x6A) Cr Value 128 (0x80) 128 (0x80) 240 (0xF0) 34 (0x22) 110 (0x6E) 146 (0x92) 16 (0x10) 222 (0xDE) Cb Value 128 (0x80) 128 (0x80) 90 (0x5A) 54 (0x36) 240 (0xF0) 16 (0x10) 166 (0xA6) 202 (0xCA) COLOR SPACE CONVERSION MATRIX Subaddress 0x03 to Subaddress 0x09 The internal color space conversion (CSC) matrix automatically performs all color space conversions based on the input mode programmed in the mode select register (Subaddress 0x01, Bits[6:4]). Table 42 and Table 43 show the options available in this matrix. An SD color space conversion from RGB-in to YPrPb-out is possible. An ED/HD color space conversion from RGB-in to YPrPb-out is not possible. Table 42. SD Color Space Conversion Options Input YCrCb YCrCb RGB RGB 1 Figure 66. ED/HD Sinc Compensation Filter Enabled 0.5 0.4 0.3 0.2 GAIN (dB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 5 10 15 20 FREQUENCY (MHz) 25 30 06400-068 -0.5 Figure 67. ED/HD Sinc Compensation Filter Disabled ED/HD TEST PATTERN COLOR CONTROLS Subaddress 0x36 to Subaddress 0x38 Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38 are used to program the output color of the internal ED/HD test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it be the lines of the cross hatch pattern or the uniform field test pattern. They are not functional as color controls for external pixel data input. The values for the luma (Y) and the color difference (Cr and Cb) signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard. Table 41 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA 770.2/ EIA770.3 (Subaddress 0x30, Bits[1:0] = 00). Output1 YPrPb RGB YPrPb RGB YPrPb/RGB Out (Reg. 0x02, Bit 5) 1 0 1 0 RGB In/YCrCb In (Reg. 0x87, Bit 7) 0 0 1 1 CVBS/YC outputs are available for all CSC combinations. Table 43. ED/HD Color Space Conversion Options Input YCrCb YCrCb RGB Output YPrPb RGB RGB YPrPb/RGB Out (Reg. 0x02, Bit 5) 1 0 0 RGB In/YCrCb In (Reg. 0x35, Bit 1) 0 0 1 ED/HD Manual CSC Matrix Adjust Feature The ED/HD manual CSC matrix adjust feature provides custom coefficient manipulation for color space conversions and is used in ED and HD modes only. The ED/HD manual CSC matrix adjust feature can be enabled using Subaddress 0x02, Bit 3. Normally, there is no need to enable this feature because the CSC matrix automatically performs the color space conversion based on the input mode chosen (ED or HD) and the input and output color spaces selected (see Table 43). For this reason, the ED/HD manual CSC matrix adjust feature is disabled by default. Rev. 0 | Page 53 of 88 ADV7344 If RGB output is selected, the ED/HD CSC matrix scalar uses the following equations: R = GY x Y + RV x Pr G = GY x Y - (GU x Pb) - (GV x Pr) B = GY x Y + BU x Pb If the ED/HD manual CSC matrix adjust feature is enabled and another input standard (such as ED) is used, the scale values for GY, GU, GV, BU, and RV must be adjusted according to this input standard color space. The user should consider that the color component conversion could use different scale values. For example, SMPTE 293M uses the following conversion: R = Y + 1.402Pr G = Y - 0.714Pr - 0.344Pb B = Y + 1.773Pb Note that subtractions are implemented in hardware. If YPrPb output is selected, the following equations are used: Y = GY x Y Pr = RV x Pr Pb = BU x Pb The programmable CSC matrix is used for external ED/HD pixel data and is not functional when internal test patterns are enabled. where: GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0]. GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6]. GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4]. BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2]. RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0]. Programming the CSC Matrix If custom manipulation of the ED/HD CSC matrix coefficients is required for a YCrCb-to-RGB color space conversion, follow the following procedure: 1. 2. 3. 4. Enable the ED/HD manual CSC matrix adjust feature (Subaddress 0x02, Bit 3). Set the output to RGB (Subaddress 0x02, Bit 5). Disable sync on PrPb (Subaddress 0x35, Bit 2). Enable sync on RGB (optional) (Subaddress 0x02, Bit 4). Upon power-up, the CSC matrix is programmed with the default values shown in Table 44. Table 44. ED/HD Manual CSC Matrix Default Values Subaddress 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Default 0x03 0xF0 0x4E 0x0E 0x24 0x92 0x7C The GY value controls the green signal output level, the BU value controls the blue signal output level, and the RV value controls the red signal output level. SD LUMA AND COLOR CONTROL Subaddress 0x9C to Subaddress 0x9F SD Y Scale, SD Cb Scale, and SD Cr Scale are three 10-bit control registers that scale the SD Y, Cb, and Cr output levels. Each of these registers represents the value required to scale the Cb or Cr level from 0.0 to 2.0 times its initial value and the Y level from 0.0 to 1.5 times its initial level. The value of these 10 bits is calculated using the following equation: Y, Cb, or Cr Scale Value = Scale Factor x 512 When the ED/HD manual CSC matrix adjust feature is enabled, the default coefficient values in Subaddress 0x03 to Subaddress 0x09 are correct for the HD color space only. The color components are converted according to the following 1080i and 720p standards (SMPTE 274M, SMPTE 296M): R = Y + 1.575Pr G = Y - 0.468Pr - 0.187Pb B = Y + 1.855Pb For example, if Scale Factor = 1.3 Y, Cb, or Cr Scale Value = 1.3 x 512 = 665.6 Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer) Y, Cb, or Cr Scale Value = 1010 0110 10b The conversion coefficients should be multiplied by 315 before being written to the ED/HD CSC matrix registers. This is reflected in the default values for GY = 0x13B, GU = 0x03B, GV = 0x093, BU = 0x248, and RV = 0x1F0. Subaddress 0x9C, SD Scale LSB Register = 0x2A Subaddress 0x9D, SD Y Scale Register = 0xA6 Subaddress 0x9E, SD Cb Scale Register = 0xA6 Subaddress 0x9F, SD Cr Scale Register = 0xA6 Note that this feature affects all interlaced output signals, that is, CVBS, Y-C, YPrPb, and RGB. Rev. 0 | Page 54 of 88 ADV7344 SD HUE ADJUST CONTROL Subaddress 0xA0 When enabled, the SD hue adjust control register (Subaddress 0xA0) is used to adjust the hue on the SD composite and chroma outputs. This feature can be enabled using Subaddress 0x87, Bit 2. Subaddress 0xA0 contains the bits required to vary the hue of the video data, that is, the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7344 provides a range of 22.5 in increments of 0.17578125. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits, respectively, of the attainable adjustment in NTSC mode. Values 0xFF and 0x01 represent the upper and lower limits, respectively, of the attainable adjustment in PAL mode. The hue adjust value is calculated using the following equation: Hue Adjust () = 0.17578125 (HCRd - 128) For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and for PAL, the setup can vary from -7.5 IRE to +15 IRE. The SD brightness control register is an 8-bit register. The seven LSBs of this 8-bit register are used to control the brightness level, which can be a positive or negative value. For example, to add +20 IRE brightness level to an NTSC signal with pedestal, write 0x28 to Subaddress 0xA1. 0 x (SD Brightness Value) = 0 x (IRE Value x 2.015631) = 0 x (20 x 2.015631) = 0 x (40.31262) 0x28 To add -7 IRE brightness level to a PAL signal, write 0x72 to Subaddress 0xA1. 0 x (SD Brightness Value) = 0 x (IRE Value x 2.075631) = 0 x (7 x 2.015631) = 0x(14.109417) 0001110b 0001110b into twos complement = 1110010b = 0x72 Table 45. Sample Brightness Control Values1 Setup Level (NTSC) with Pedestal 22.5 IRE 15 IRE 7.5 IRE 0 IRE 1 where: HCRd = hue adjust control register (decimal) For example, to adjust the hue by +4, write 0x97 to the hue adjust control register: 4 + 128 151d = 0 x 97 0.17578125 where the sum is rounded to the nearest integer. To adjust the hue by -4, write 0x69 to the hue adjust control register. -4 + 128 105d = 0 x 69 0.17578125 Setup Level (NTSC) Without Pedestal 15 IRE 7.5 IRE 0 IRE -7.5 IRE Setup Level (PAL) 15 IRE 7.5 IRE 0 IRE -7.5 IRE Brightness Control Value 0x1E 0x0F 0x00 0x71 Values in the range of 0x3F to 0x44 could result in an invalid output signal. SD INPUT STANDARD AUTO DETECTION Subaddress 0x87, Bit 5 The ADV7344 includes an SD input standard auto-detect feature. This SD feature can be enabled by setting Subaddress 0x87, Bit 5 to 1. When enabled, the ADV7344 can automatically identify an NTSC or PAL B/D/G/H/I input stream. The ADV7344 automatically updates the subcarrier frequency registers with the appropriate value for the identified standard. The ADV7344 is also configured to correctly encode the identified standard. The SD standard bits (Subaddress 0x80, Bits[1:0]) and the subcarrier frequency registers are not updated to reflect the identified standard. All registers retain their default or userdefined values. where the sum is rounded to the nearest integer. SD BRIGHTNESS DETECT Subaddress 0xBA The ADV7344 allows monitoring of the brightness level of the incoming video data. The SD brightness detect register (Subaddress 0xBA) is a read-only register. SD BRIGHTNESS CONTROL Subaddress 0xA1, Bits[6:0] When this feature is enabled, the SD brightness/WSS control register (Subaddress 0xA1) is used to control brightness by adding a programmable setup level onto the scaled Y data. This feature can be enabled using Subaddress 0x87, Bit 3. NTSC WITHOUT PEDESTAL 100 IRE +7.5 IRE 0 IRE NO SETUP VALUE ADDED POSITIVE SETUP VALUE ADDED NEGATIVE SETUP VALUE ADDED -7.5 IRE 06400-069 Figure 68. Examples of Brightness Control Values Rev. 0 | Page 55 of 88 ADV7344 DOUBLE BUFFERING Subaddress 0x33, Bit 7 for ED/HD, Subaddress 0x88, Bit 2 for SD Double-buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not made during active video, but take effect prior to the start of the active video on the next field. Double buffering can be activated on the following ED/HD registers using Subaddress 0x33, Bit 7: ED/HD Gamma A and Gamma B curves, and ED/HD CGMS registers. Double buffering can be activated on the following SD registers using Subaddress 0x88, Bit 2: SD Gamma A and Gamma B curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD closed captioning, and SD Macrovision Bits[5:0] (Subaddress 0xE0, Bits[5:0]). In Case B of Figure 69, the video output signal is reduced. The absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. The overall gain of the signal is reduced from the reference signal. The range of this feature is specified for 7.5% of the nominal output from the DACs. For example, if the output current of the DAC is 4.33 mA, the DAC gain control feature can change this output current from 4.008 mA (-7.5%) to 4.658 mA (+7.5%). The reset value of the control registers is 0x00, that is, nominal DAC current is output. Table 46 is an example of how the output current of the DACs varies for a nominal 4.33 mA output current. Table 46. DAC Gain Control Reg. 0x0A or Reg.0x0B 0100 0000 (0x40) 0011 1111 (0x3F) 0011 1110 (0x3E) ... ... 0000 0010 (0x02) 0000 0001 (0x01) 0000 0000 (0x00) 1111 1111 (0xFF) 1111 1110 (0xFE) ... ... 1100 0010 (0xC2) 1100 0001 (0xC1) 1100 0000 (0xC0) DAC Current (mA) 4.658 4.653 4.648 ... ... 4.43 4.38 4.33 4.25 4.23 ... ... 4.018 4.013 4.008 % Gain 7.5000% 7.3820% 7.3640% ... ... 0.0360% 0.0180% 0.0000% -0.0180% -0.0360% ... ... -7.3640% -7.3820% -7.5000% Note PROGRAMMABLE DAC GAIN CONTROL Subaddress 0x0A to Subaddress 0x0B It is possible to adjust the DAC output signal gain up or down from its absolute level. This is illustrated in Figure 69. DAC 4 to DAC 6 are controlled by Register 0x0A. DAC 1 to DAC 3 are controlled by Register 0x0B. CASE A GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0A, 0x0B 700mV Reset value, nominal GAMMA CORRECTION 300mV CASE B 700mV NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0A, 0x0B Subaddress 0x44 to Subaddress 0x57 for ED/HD, Subaddress 0xA6 to Subaddress 0xB9 for SD Generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and output brightness level (as perceived on a CRT). It can also be applied wherever nonlinear processing is used. Gamma correction uses the function SignalOUT = (SignalIN) 300mV 06400-070 where = is the gamma correction factor. Gamma correction is available for SD and ED/HD video. For both variations, there are 20, 8-bit registers. They are used to program the Gamma Correction Curve A and Gamma Correction Curve B. ED/HD gamma correction is enabled using Subaddress 0x35, Bit 5. ED/HD Gamma Correction Curve A is programmed at Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma Correction Curve B is programmed at Subaddress 0x4E to Subaddress 0x57. Figure 69. Programmable DAC Gain--Positive and Negative Gain In Case A of Figure 69, the video output signal is gained. The absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. The overall gain of the signal is increased from the reference signal. Rev. 0 | Page 56 of 88 ADV7344 SD gamma correction is enabled using Subaddress 0x88, Bit 6. SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9. Gamma correction is performed on the luma data only. The user can choose one of two correction curves, Curve A or Curve B. Only one of these curves can be used at a time. For ED/HD gamma correction, curve selection is controlled using Subaddress 0x35, Bit 4. For SD gamma correction, curve selection is controlled using Subaddress 0x88, Bit 7. The shape of the gamma correction curve is controlled by defining the curve response at 10 different locations along the curve. By altering the response at these locations, the shape of the gamma correction curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the curve has a total length of 256 points, the 10 programmable locations are at points 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed. From curve locations 16 to 240, the values at the programmable locations and, therefore, the response of the gamma correction curve, should be calculated to produce the following result: xDESIRED = (xINPUT) To program the gamma correction registers, calculate the 10 programmable curve values using the following formula: n - 16 n = 240 - 16 x (240 - 16) + 16 where: n is the value to be written into the gamma correction register for point n on the gamma correction curve. n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224. is the gamma correction factor. For example, setting = 0.5 for all programmable curve data points results in the following yn values: y24 = [(8/224)0.5 x 224] + 16 = 58 y32 = [(16/224)0.5 x 224] + 16 = 76 y48 = [(32/224)0.5 x 224] + 16 = 101 y64 = [(48/224)0.5 x 224] + 16 = 120 y80 = [(64/224)0.5 x 224] + 16 = 136 y96 = [(80/224)0.5 x 224] + 16 = 150 y128 = [(112/224)0.5 x 224] + 16 = 174 y160 = [(144/224)0.5 x 224] + 16 = 195 y192 = [(176/224)0.5 x 224] + 16 = 214 y224 = [(208/224)0.5 x 224] + 16 = 232 where: xDESIRED is the desired gamma corrected output. xINPUT is the linear input signal. is gamma correction factor. where the sum of each equation is rounded to the nearest integer. The gamma curves in Figure 70 and Figure 71 are examples only; any user-defined curve in the range from 16 to 240 is acceptable. 300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT 300 GAMMA CORRECTED AMPLITUDE GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR VARIOUS GAMMA VALUES 250 GAMMA CORRECTED AMPLITUDE SIGNAL OUTPUT 200 250 0.3 0.5 150 AL GN T PU IN 0.5 200 150 100 SIGNAL INPUT 1.5 100 SI 50 1.8 50 0 50 100 150 LOCATION 200 250 Figure 70. Signal Input (Ramp) and Signal Output for Gamma 0.5 Figure 71. Signal Input (Ramp) and Selectable Output Curves Rev. 0 | Page 57 of 88 06400-072 0 50 100 150 LOCATION 200 250 06400-071 0 0 ADV7344 ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS Subaddress 0x40, Subaddress 0x58 to Subaddress 0x5D There are three filter modes available on the ADV7344, a sharpness filter mode and two adaptive filter modes. The derivative of the incoming signal is compared to the three programmable threshold values: ED/HD Adaptive Filter Threshold A, B, and C (Subaddress 0x5B, Subaddress 0x5C, and Subaddress 0x5D, respectively). The recommended threshold range is 16 to 235, although any value in the range of 0 to 255 can be used. The edges can then be attenuated with the settings in the ED/HD Adaptive Filter Gain 1, 2, and 3 registers (Subaddress 0x58, Subaddress 0x59 and Subaddress 0x5A, respectively), and the ED/HD sharpness filter gain register (Subaddress 0x40). There are two adaptive filter modes available. The mode is selected using the ED/HD adaptive filter mode control (Subaddress 0x35, Bit 6): * Mode A is used when the ED/HD adaptive filter mode control is set to 0. In this case, Filter B (LPF) is used in the adaptive filter block. In addition, only the programmed values for Gain B in the ED/HD sharpness filter gain register and ED/HD Adaptive Filter Gain 1, 2, and 3 registers are applied when needed. The Gain A values are fixed and cannot be changed. Mode B is used when ED/HD adaptive filter mode control is set to 1. In this mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the ED/HD sharpness filter gain register and ED/HD Adaptive Filter Gain 1, 2, and 3 registers become active when needed. ED/HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in Figure 72, the ED/HD sharpness filter must be enabled (Subaddress 0x31, Bit 7) and the ED/HD adaptive filter must be disabled (Subaddress 0x35, Bit 7). To select one of the 256 individual responses, the corresponding gain values, which range from -8 to +7 for each filter, must be programmed into the ED/HD sharpness filter gain register at Subaddress 0x40. ED/HD Adaptive Filter Mode The ED/HD Adaptive Filter Threshold A, B, and C registers, the ED/HD Adaptive Filter Gain 1, 2, and 3 registers, and the ED/HD sharpness filter gain register are used in adaptive filter mode. To activate the adaptive filter control, the ED/HD sharpness filter and the ED/HD adaptive filter must be enabled (Subaddress 0x31, Bit 7, and Subaddress 0x35, Bit 7, respectively). * 1.4 1.3 1.2 MAGNITUDE MAGNITUDE 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka) 0.5 FREQUENCY (MHz) FILTER B RESPONSE (Gain Kb) MAGNITUDE RESPONSE (Linear Scale) 1.5 SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK 1.5 1.6 1.5 1.4 1.3 1.2 1.1 1.0 INPUT SIGNAL: STEP 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 2 FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb = 7 Figure 72. ED/HD Sharpness and Adaptive Filter Control Block Rev. 0 | Page 58 of 88 06400-073 6 8 4 10 FREQUENCY (MHz) 12 ADV7344 a R2 1 d b R4 R1 e c 1 R2 f CH1 500mV REF A 500mV 4.00s M 4.00s 1 9.99978ms CH1 ALL FIELDS CH1 500mV REF A 500mV 4.00s 1 M 4.00s 9.99978ms CH1 ALL FIELDS Figure 73. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The ED/HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings in Table 47 were used to achieve the results shown in Figure 73. Input data was generated by an external signal source. Table 47. ED/HD Sharpness Control Subaddress 0x00 0x01 0x02 0x30 0x31 0x40 0x40 0x40 0x40 0x40 0x40 1 Adaptive Filter Control Application The register settings in Table 48 are used to obtain the results shown in Figure 75, that is, to remove the ringing on the input Y signal, as shown in Figure 74. Input data is generated by an external signal source. Table 48. Register Settings for Figure 75 Subaddress 0x00 0x01 0x02 0x30 0x31 0x35 0x40 0x58 0x59 0x5A 0x5B 0x5C 0x5D Register Setting 0xFC 0x38 0x20 0x00 0x81 0x80 0x00 0xAC 0x9A 0x88 0x28 0x3F 0x64 Register Setting 0xFC 0x10 0x20 0x00 0x81 0x00 0x08 0x04 0x40 0x80 0x22 Reference1 a b c d e f See Figure 73. Rev. 0 | Page 59 of 88 06400-074 ADV7344 In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal is subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise. Otherwise, if the level exceeds the threshold, now identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) is added to the original signal to boost high frequency components and sharpen the video image. 06400-075 Figure 74. Input Signal to ED/HD Adaptive Filter In MPEG systems, it is common to process the video information in blocks of 8 pixels x 8 pixels for MPEG2 systems, or 16 pixels x 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset. The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing. 06400-076 DNR MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN Figure 75. Output Signal from ED/HD Adaptive Filter (Mode A) When changing the adaptive filter mode to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 76 can be obtained. NOISE SIGNAL PATH CORING GAIN DATA CORING GAIN BORDER INPUT FILTER BLOCK FILTER OUTPUT < THRESHOLD? FILTER OUTPUT > THRESHOLD MAIN SIGNAL PATH - + SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL DNR OUT Y DATA INPUT DNR SHARPNESS MODE 06400-077 DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN Figure 76. Output Signal from ED/HD Adaptive Filter (Mode B) SD DIGITAL NOISE REDUCTION Subaddress 0xA3 to Subaddress 0xA5 Digital noise reduction (DNR) is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). There are two DNR modes available, DNR mode and DNR sharpness mode. Y DATA INPUT NOISE SIGNAL PATH CORING GAIN DATA CORING GAIN BORDER INPUT FILTER BLOCK FILTER OUTPUT > THRESHOLD? FILTER OUTPUT < THRESHOLD MAIN SIGNAL PATH + DNR OUT 06400-078 ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL + Figure 77. SD DNR Block Diagram Rev. 0 | Page 60 of 88 ADV7344 Coring Gain Border--Subaddress 0xA3, Bits[3:0] These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal. Block Size Control--Subaddress 0xA4, Bit 7 This bit is used to select the size of the data blocks to be processed. Setting the block size control function to Logic 1 defines a 16 pixel x 16 pixel data block, and Logic 0 defines an 8 pixel x 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz. DNR Input Select Control--Subaddress 0xA5, Bits[2:0] Three bits are assigned to select the filter, which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that is DNR processed. Figure 80 shows the filter responses selectable with this control. 1.0 FILTER D 0.8 MAGNITUDE Coring Gain Data--Subaddress 0xA3, Bits[7:4] These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal. APPLY DATA CORING GAIN APPLY BORDER CORING GAIN FILTER C 0.6 0.4 FILTER B 0.2 FILTER A 06400-081 OXXXXXXOOXXXXXXO OFFSET CAUSED BY VARIATIONS IN INPUT TIMING 06400-079 0 0 1 2 3 4 FREQUENCY (MHz) 5 6 OXXXXXXOOXXXXXXO Figure 80. SD DNR Input Select DNR27 - DNR24 = 0x01 OXXXXXXOOXXXXXXO DNR Mode Control--Subaddress 0xA5, Bit 4 This bit controls the DNR mode selected. Logic 0 selects DNR mode; Logic 1 selects DNR sharpness mode. DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, because this data is assumed to be valid data and not noise. The overall effect is that the signal is boosted (similar to using the extended SSAF filter). Figure 78. SD DNR Offset Control DNR Threshold--Subaddress 0xA4, Bits[5:0] These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value. Border Area--Subaddress 0xA4, Bit 6 When this bit is set to Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz. 720 x 485 PIXELS (NTSC) 2-PIXEL BORDER DATA DNR Block Offset Control--Subaddress 0xA5, Bits[7:4] Four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. 8 x 8 PIXEL BLOCK 8 x 8 PIXEL BLOCK Figure 79. SD DNR Border Area 06400-080 Rev. 0 | Page 61 of 88 ADV7344 SD ACTIVE VIDEO EDGE CONTROL Subaddress 0x82, Bit 7 The ADV7344 is able to control fast rising and falling signals at the start and end of active video in order to minimize ringing. When the active video edge control feature is enabled (Subaddress 0x82, Bit 7 = 1), the first three pixels and the last LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE 100 IRE 87.5 IRE 50 IRE 0 IRE 12.5 IRE 0 IRE three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. At the start of active video, the first three pixels are multiplied by 1/8, 1/2, and 7/8, respectively. Approaching the end of active video, the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively. All other active video pixels pass through unprocessed. LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED Figure 81. Example of Active Video Edge Functionality VOLTS IRE:FLT 100 0.5 50 0 0 -50 0 2 4 6 8 10 12 Figure 82. Example of Video Output with Subaddress 0x82, Bit 7 = 0 VOLTS IRE:FLT 100 0.5 50 0 0 -50 -2 0 2 4 6 8 10 12 Figure 83. Example of Video Output with Subaddress 0x82, Bit 7 = 1 Rev. 0 | Page 62 of 88 06400-084 F2 L135 06400-083 F2 L135 06400-082 ADV7344 EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For synchronization purposes, the ADV7344 is able to accept either time codes embedded in the input pixel data or external synchronization signals provided on the S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK pins (see Table 49). It is also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 50 to Table 52). Table 49. Timing Synchronization Signal Input Options Signal SD HSYNC In SD VSYNC In ED/HD HSYNC In ED/HD VSYNC In ED/HD BLANK In 1 Pin S_HSYNC S_VSYNC P_HSYNC P_VSYNC P_BLANK Condition SD Slave Timing Mode 1, 2, or 3 selected (Subaddress 0x8A[2:0]).1 SD Slave Timing Mode 1, 2, or 3 selected (Subaddress 0x8A[2:0]).1 ED/HD Timing Sync. Inputs enabled (Subaddress 0x30, Bit 2 = 0). ED/HD Timing Sync. Inputs enabled (Subaddress 0x30, Bit 2 = 0). SD and ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02[7:6] = 00). Table 50. Timing Synchronization Signal Output Options Signal SD HSYNC Out SD VSYNC Out ED/HD HSYNC Out ED/HD VSYNC Out 1 Pin S_HSYNC S_VSYNC S_HSYNC S_VSYNC Condition SD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 6 = 1).1 SD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 6 = 1).1 ED/HD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 7 = 1). ED/HD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 7 = 1). ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02, Bit 7 = 0). Table 51. HSYNC Output Control1 ED/HD Input Sync Format (0x30, Bit 2) x x 0 1 x 1 ED/HD HSYNC Control (0x34, Bit 1) x x 0 0 1 ED/HD Sync Output Enable (0x02, Bit 7) 0 0 1 1 1 SD Sync Output Enable (0x02, Bit 6) 0 1 x x x Signal on S_HSYNC Pin Tristate. Pipelined SD HSYNC. Pipelined ED/HD HSYNC. Pipelined ED/HD HSYNC based on AV Code H bit. Pipelined ED/HD HSYNC based on horizontal counter. Duration - See Appendix 5--SD Timing. As per HSYNC timing. Same as line blanking interval. Same as embedded HSYNC. In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video. Table 52. VSYNC Output Control 1 ED/HD Input Sync Format (0x30, Bit 2) x x 0 1 1 x x ED/HD VSYNC Control (0x34, Bit 2) X X 0 0 0 1 1 ED/HD Sync Output Enable (0x02, Bit 7) 0 0 1 1 1 1 1 SD Sync Output Enable (0x02, Bit 6) 0 1 x x x x x Video Standard x Interlaced x All HD interlaced standards All ED/HD progressive standards All ED/HD standards except 525p 525p Signal on S_VSYNC Pin Tristate. Pipelined SD VSYNC/Field. Pipelined ED/HD VSYNC or field signal. Pipelined field signal based on AV Code F bit. Pipelined VSYNC based on AV Code V bit. Pipelined ED/HD VSYNC based on vertical counter. Pipelined ED/HD VSYNC based on vertical counter. Duration - See Appendix 5-- SD Timing. As per VSYNC or field signal timing. Field. Vertical blanking interval. Aligned with serration lines. Vertical blanking interval. 1 In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video. Rev. 0 | Page 63 of 88 ADV7344 LOW POWER MODE Subaddress 0x0D, Bits[2:0] For power sensitive applications, the ADV7344 supports an Analog Devices Inc. proprietary low power mode of operation on DAC 1, DAC 2, and DAC 3. To utilize this low power mode, these DACs must be operating in full-drive mode (RSET = 510 , RL = 37.5 ). Low power mode is not available in low drive mode (RSET = 4.12 k, RL = 300 ). Low power mode can be independently enabled or disabled on DAC 1, DAC 2, and DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is disabled by default on each DAC. In low power mode, DAC current consumption is content dependent. On a typical video stream, it can be reduced by as much as 40%. For applications requiring the highest possible video performance, low power mode should be disabled. With this feature enabled, the cable detection circuitry monitors DAC 1 and/or DAC 2 once per frame. If they are unconnected, some or all of the DACs automatically power down. Which DAC or DACs are powered down depends on the selected output configuration. For CVBS/YC output configurations, if DAC 1 is unconnected, only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and DAC 3 power down. For YPrPb and RGB output configurations, if DAC 1 is unconnected, all three DACs power down. DAC 2 is not monitored for YPrPb and RGB output configurations. Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable is detected, the appropriate DAC or DACs remain powered up for the duration of the frame. If no cable is detected, the appropriate DAC or DACs power down until the next frame when the process is repeated. CABLE DETECTION Subaddress 0x10 The ADV7344 includes an Analog Devices Inc. proprietary cable detection feature. The cable detection feature is available on DAC 1 and DAC 2, while operating in full-drive mode (RSET1 = 510 , RL1 = 37.5 , assuming a connected cable). The feature is not available in low drive mode (RSET = 4.12 k, RL = 300 ). For a DAC to be monitored, the DAC must be powered up in Subaddress 0x00. The cable detection feature can be used with all SD, ED, and HD video standards. It is available for all output configurations, that is, CVBS, YC, YPrPb, and RGB output configurations. For CVBS/YC output configurations, both DAC 1 and DAC 2 are monitored, that is, the CVBS and YC luma outputs are monitored. For YPrPb and RGB output configurations, only DAC 1 is monitored, that is, the luma or green output is monitored. Once per frame, the ADV7344 monitors DAC 1 and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1, respectively. If a cable is detected on one of the DACs, the relevant bit is set to 0. If not, the bit is set to 1. PIXEL AND CONTROL PORT READBACK Subaddress 0x12 to Subaddress 0x16 The ADV7344 supports the readback of most digital inputs via the I2C/SPI MPU port. This feature is useful for board-level connectivity testing with upstream devices. The pixel port (S[9:0], Y[9:0], and C[9:0]), the control port (S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC and P_BLANK), and the SFL/MISO pin are available for readback via the MPU port. The readback registers are located at Subaddress 0x12 to Subaddress 0x16. When using this feature, a clock signal should be applied to the CLKIN_A pin in order to register the levels applied to the input pins. RESET MECHANISM Subaddress 0x17, Bit 1 The ADV7344 has a software reset accessible via the I2C/SPI MPU port. A software reset is activated by writing a 1 to Subaddress 0x17, Bit 1. This resets all registers to their default values. This bit is self-clearing, that is, after a 1 has been written to the bit, the bit automatically returns to 0. When operating in SPI mode, a software reset does not cause the device to revert to I2C mode. For this to occur, the ADV7344 needs to be powered down. The ADV7344 includes a power-on reset (POR) circuit to ensure correct operation after power-up. DAC AUTO POWER-DOWN Subaddress 0x10, Bit 4 For power sensitive applications, a DAC auto power-down feature can be enabled using Subaddress 0x10, Bit 4. This feature is only available when the cable detection feature is enabled. Rev. 0 | Page 64 of 88 ADV7344 PRINTED CIRCUIT BOARD LAYOUT AND DESIGN DAC CONFIGURATIONS The ADV7344 contains six DACs. All six DACs can be configured to operate in low drive mode. Low drive mode is defined as 4.33 mA full-scale current into a 300 load, RL. DAC 1, DAC 2, and DAC 3 can also be configured to operate in full-drive mode. Full-drive mode is defined as 34.7 mA fullscale current into a 37.5 load, RL. Full-drive is the recommended mode of operation for DAC 1, DAC 2, and DAC 3. The ADV7344 contains two RSET pins. A resistor connected between the RSET1 pin and AGND is used to control the fullscale output current and, therefore, the DAC output voltage levels of DAC 1, DAC 2, and DAC 3. For low drive operation, RSET1 must have a value of 4.12 k, and RL must have a value of 300 . For full-drive operation, RSET1 must have a value of 510 , and RL must have a value of 37.5 . A resistor connected between the RSET2 pin and AGND is used to control the full-scale output current and, therefore, the DAC output voltage levels of DAC 4, DAC 5, and DAC 6. RSET2 must have a value of 4.12 k, and RL must have a value of 300 (that is, low drive operation only). The resistors connected to the RSET1 and RSET2 pins should have a 1% tolerance. The ADV7344 contains two compensation pins, COMP1 and COMP2. A 2.2 nF compensation capacitor should be connected from each of these pins to VAA. For applications requiring an output buffer and reconstruction filter, the ADA4430-1, ADA4411-3, and ADA4410-6 integrated video filter buffers should be considered. Table 53. ADV7344 Output Rates Input Mode (0x01, Bits[6:4]) SD Only ED Only HD Only PLL Control (0x00, Bit 1) Off On Off On Off On Output Rate (MHz) 27 (2x) 216 (16x) 27 (1x) 216 (8x) 74.25 (1x) 297 (4x) Table 54. Output Filter Requirements Cutoff Frequency (MHz) >6.5 >6.5 >12.5 >12.5 >30 >30 Attenuation -50 dB @ (MHz) 20.5 209.5 14.5 203.5 44.25 267 Application SD SD ED ED HD HD Oversampling 2x 16x 1x 8x 1x 4x 10H DAC OUTPUT 600 22pF 600 3 1 4 75 VOLTAGE REFERENCE The ADV7344 contains an on-chip voltage reference that can be used as a board-level voltage reference via the VREF pin. Alternatively, the ADV7344 can be used with an external voltage reference by connecting the reference source to the VREF pin. For optimal performance, an external voltage reference such as the AD1580 should be used with the ADV7344. If an external voltage reference is not used, a 0.1 F capacitor should be connected from the VREF pin to VAA. BNC OUTPUT 560 Figure 84. Example of Output Filter for SD, 16x Oversampling 4.7H DAC OUTPUT 6.8pF 600 6.8pF 600 4 3 75 1 BNC OUTPUT 560 An output buffer is necessary on any DAC that operates in low drive mode (RSET = 4.12 k, RL = 300 ). Analog Devices, Inc. produces a range of op amps suitable for this application, for example, the AD8061. For more information about line driver buffering circuits, see the relevant op amp data sheet. An optional reconstruction (anti-imaging) low-pass filter (LPF) may be required on the ADV7344 DAC outputs if the ADV7344 is connected to a device that requires this filtering. The filter specifications vary with the application. The use of 16x (SD), 8x (ED), or 4x (HD) oversampling can remove the requirement for a reconstruction filter altogether. Figure 85. Example of Output Filter for ED, 8x Oversampling DAC OUTPUT 3 300 4 1 75 390nH 3 BNC OUTPUT 1 33pF 33pF 75 4 500 500 Figure 86. Example of Output Filter for HD, 4x Oversampling Rev. 0 | Page 65 of 88 06400-087 06400-086 VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER 560 06400-085 560 ADV7344 0 -10 MAGNITUDE (dB) -20 -30 CIRCUIT FREQUENCY RESPONSE 0 24n -30 21n -60 18n -90 PHASE (Degrees) 15n -120 12n -150 GROUP DELAY (Seconds) -60 -70 -80 1M 9n -180 6n -210 3n -240 0 1G PRINTED CIRCUIT BOARD (PCB) LAYOUT The ADV7344 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system-level design so that optimal performance is achieved. The layout should be optimized for lowest noise on the ADV7344 power and ground planes by shielding the digital inputs and providing good power supply decoupling. It is recommended to use a 4-layer printed circuit board with ground and power planes separating the signal trace layer and the solder side layer. 06400-088 GAIN (dB) -40 -50 10M 100M FREQUENCY (Hz) Figure 87. Output Filter Plot for SD, 16x Oversampling Component Placement 0 -10 MAGNITUDE (dB) -20 -30 320 14n 240 160 80 8n -60 -70 -80 -90 1M 0 6n -80 4n -160 2n -240 0 1G 12n 10n -50 CIRCUIT FREQUENCY RESPONSE 480 18n 400 16n Component placement should be carefully considered to separate noisy circuits, such as clock signals and high speed digital circuitry from analog circuitry. The external loop filter components and components connected to the COMP, VREF, and RSET pins should be placed as close as possible to and on the same side of the PCB as the ADV7344. Adding vias to the PCB to get the components closer to the ADV7344 is not recommended. It is recommended that the ADV7344 be placed as close as possible to the output connector, with the DAC output traces as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV7344. The termination resistors should overlay the PCB ground plane. External filter and buffer components connected to the DAC outputs should be placed as close as possible to the ADV7344 to minimize the possibility of noise pickup from neighboring circuitry, and to minimize the effect of trace capacitance on output bandwidth. This is particularly important when operating in low drive mode (RSET = 4.12 k, RL = 300 ). 06400-089 GAIN (dB) -40 GROUP DELAY (Seconds) PHASE (Degrees) 10M 100M FREQUENCY (Hz) Figure 88. Output Filter Plot for ED, 8x Oversampling 0 CIRCUIT FREQUENCY RESPONSE PHASE (Degrees) MAGNITUDE (dB) 200 -10 GROUP DELAY (Seconds) GAIN (dB) 120 -20 40 PHASE (Degrees) Power Supplies It is recommended that a separate regulated supply be provided for each power domain (VAA, VDD, VDD_IO, and PVDD). For optimal performance, linear regulators rather than switch mode regulators should be used. If switch mode regulators must be used, care must be taken with regard to the quality of the output voltage in terms of ripple and noise. This is particularly true for the VAA and PVDD power domains. Each power supply should be individually connected to the system power supply at a single point through a suitable filtering device, such as a ferrite bead. -30 -40 -40 -120 1 10 FREQUENCY (MHz) 100 Figure 89. Output Filter Plot for HD, 4x Oversampling Rev. 0 | Page 66 of 88 06400-090 -50 -200 ADV7344 Power Supply Decoupling It is recommended that each power supply pin be decoupled with 10 nF and 0.1 F ceramic capacitors. The VAA, PVDD, VDD_IO, and both VDD pins should be individually decoupled to ground. The decoupling capacitors should be placed as close as possible to the ADV7344 with the capacitor leads kept as short as possible to minimize lead inductance. A 1 F tantalum capacitor is recommended across the VAA supply in addition to the 10 nF and 0.1 F ceramic capacitors. Due to the high clock rates used, avoid long clock traces to the ADV7344 to minimize noise pickup. Any pull-up termination resistors for the digital inputs should be connected to the VDD power supply. Any unused digital inputs should be tied to ground. Analog Signal Interconnect DAC output traces should be treated as transmission lines with appropriate measures taken to ensure optimal performance (for example, impedance matched traces). The DAC output traces should be kept as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV7344. To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the traces connected to the DAC output pins. Adding ground traces between the DAC output traces is also recommended. Power Supply Sequencing The ADV7344 is robust to all power supply sequencing combinations. Any particular sequence can be used. Digital Signal Interconnect The digital signal traces should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal traces should not overlay the VAA or PVDD power planes. Rev. 0 | Page 67 of 88 ADV7344 TYPICAL APPLICATION CIRCUIT FERRITE BEAD VDD_IO 33F 10F 0.1F GND_IO 0.01F GND_IO VDD_IO POWER SUPPLY DECOUPLING NOTES 1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP, RSET, VREF AND DAC OUTPUT PINS SHOULD BE LOCATED CLOSE TO AND ON THE SAME SIDE OF THE PCB AS THE ADV7344. 2. WHEN OPERATING IN I2C MODE, THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB/SPI_SS PIN: ALSB/SPI_SS = 0, I2C DEVICE ADDRESS = 0xD4 ALSB/SPI_SS = 1, I2C DEVICE ADDRESS = 0xD6 3. THE RESISTORS CONNECTED TO THE RSET PINS SHOULD HAVE A 1% TOLERANCE. PVDD (1.8V) GND_IO GND_IO FERRITE BEAD 33F 10F 0.1F PGND 0.01F PGND PGND PGND FERRITE BEAD VAA 33F 10F PVDD POWER SUPPLY DECOUPLING 0.1F AGND 0.01F AGND 1F VDD (1.8V) AGND AGND FERRITE BEAD 33F DGND 10F DGND VAA POWER SUPPLY AGND DECOUPLING VDD POWER SUPPLY DECOUPLING FOR EACH POWER PIN VAA 0.1F DGND 0.01F DGND VAA 2.2nF VDD VDD VAA PVDD 2.2nF VAA 1.1k 1.235V 0.1F Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 VDD_IO COMP1 COMP2 VREF RSET1 RSET2 4.12k AGND DAC 1 DAC 2 DAC 3 75 AGND 75 AGND 75 510 AGND OPTIONAL LPF OPTIONAL. IF THE INTERNAL VOLTAGE REFERENCE IS USED, A 0.1F CAPACITOR SHOULD BE CONNECTED FROM VREF TO VAA. AD1580 AGND ADV7344 DAC 1 DAC 2 DAC 3 OPTIONAL LPF OPTIONAL LPF DACs 1 TO 3 FULL DRIVE OPTION PIXEL PORT INPUTS AGND DACs 1 TO 3 LOW DRIVE OPTION OPTIONAL LPF DAC 4 + - 300 510 AGND 510 300 AGND OPTIONAL LPF DAC 5 + - 300 510 AGND 510 300 AGND OPTIONAL LPF DAC 6 + - 300 AGND 510 AGND 510 AD8061 +V -V RSET1 75 DAC 4 4.12k AGND OPTIONAL LPF DAC 1 + - AD8061 +V -V 75 DAC 1 S_HSYNC S_VSYNC CONTROL INPUTS/OUTPUTS P_HSYNC P_VSYNC P_BLANK CLKIN_A CLKIN_B SDA/SCLK SCL/MOSI SFL/MISO ALSB/SPI_SS AD8061 +V -V 75 DAC 5 DAC 2 510 AGND OPTIONAL LPF + - CLOCK INPUTS AD8061 +V -V 75 DAC 2 MPU PORT INPUTS/OUTPUTS EXTERNAL LOOP FILTER PVDD 150nF 12nF 150nF 12nF AD8061 +V -V 75 DAC 6 DAC 3 510 AGND OPTIONAL LPF + - 300 EXT_LF1 170 EXT_LF1 170 AGND PGND DGND DGND GND_IO 510 AGND 510 AGND AD8061 +V -V 75 DAC 3 LOOP FILTER COMPONENTS SHOULD BE LOCATED CLOSE TO THE EXT_LF PIN AND ON THE SAME SIDE OF THE PCB AS THE ADV7344. 510 AGND 510 AGND 06400-091 AGND PGND DGND DGND GND_IO Figure 90. ADV7344 Typical Application Circuit Rev. 0 | Page 68 of 88 ADV7344 APPENDIX 1--COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV7344 supports copy generation management system (CGMS) conforming to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both. SD CGMS data can only be transmitted when the ADV7344 is configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 91). When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i CGMS data is applied to Line 19 and Line 582 of the luminance vertical blanking interval. The HD CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV7344 also supports CGMS Type B packets in HD mode (720p and 1080i) in accordance with CEA-805-A. When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 720p CGMS data is applied to Line 23 of the luminance vertical blanking interval. When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 1080i CGMS data is applied to Line 18 and Line 581 of the luminance vertical blanking interval. The HD CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E. ED CGMS Subaddress 0x41 to Subaddress 0x43 Subaddress 0x5E to Subaddress 0x6E 525p The ADV7344 supports copy generation management system (CGMS) in 525p mode in accordance with EIAJ CPR-1204-1. When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p CGMS data is inserted on Line 41. The 525p CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV7344 also supports CGMS Type B packets in 525p mode in accordance with CEA-805-A. When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 525p CGMS Type B data is inserted on Line 40. The 525p CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E. CGMS CRC FUNCTIONALITY If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS data bits, C19 to C14, which comprise the 6-bit CRC check sequence, are automatically calculated on the ADV7344. This calculation is based on the lower 14 bits (C13 to C0) of the data in the CGMS data registers, and the result is output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If SD CGMS CRC or ED/HD CGMS CRC are disabled, all 20 bits (C19 to C0) are output directly from the CGMS registers (CRC must be calculated by the user manually). If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is enabled, the upper six CGMS Type B data bits (P122 to P127) that comprise the 6-bit CRC check sequence are automatically calculated on the ADV7344. This calculation is based on the lower 128 bits (H0 to H5 and P0 to P121) of the data in the CGMS Type B data registers. The result is output with the remaining 128 bits to form the complete 134 bits of the CGMS Type B data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5 and P0 to P127) are output directly from the CGMS Type B registers (CRC must be calculated by the user manually). 625p The ADV7344 supports copy generation management system (CGMS) in 625p mode in accordance with IEC 62375 (2004). When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p CGMS data is inserted on Line 43. The 625p CGMS data registers are at Subaddress 0x42 and Subaddress 0x43. HD CGMS Subaddress 0x41 to Subaddress 0x43 Subaddress 0x5E to Subaddress 0x6E The ADV7344 supports copy generation management system (CGMS) in HD mode (720p and 1080i) in accordance with EIAJ CPR-1204-2. When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p CGMS data is applied to Line 24 of the luminance vertical blanking interval. Rev. 0 | Page 69 of 88 ADV7344 +100 IRE REF +70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0 IRE -40 IRE 11.2s CRC SEQUENCE 2.235s 20ns Figure 91. Standard Definition CGMS Waveform CRC SEQUENCE +700mV REF 70% 10% C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV -300mV 5.8s 0.15s 6T 21.2s 0.22s 22T 06400-093 BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20 T = 1/(fH x 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T 30ns Figure 92. Enhanced Definition (525p) CGMS Waveform PEAK WHITE R = RUN-IN S = START CODE 500mV 25mV R S C0 LSB C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 MSB SYNC LEVEL 13.7s 06400-094 5.5s 0.125s Figure 93. Enhanced Definition (625p) CGMS Waveform +700mV REF 70% 10% CRC SEQUENCE BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV -300mV 4T 3.128s 90ns T 30ns 17.2s 160ns 22T T = 1/(fH x 1650/58) = 781.93ns fH = HORIZONTAL SCAN FREQUENCY 1H 06400-092 49.1s 0.5s Figure 94. High Definition (720p) CGMS Waveform Rev. 0 | Page 70 of 88 06400-095 ADV7344 +700mV REF 70% 10% BIT 1 BIT 2 CRC SEQUENCE BIT 20 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV -300mV 4T 4.15s 60ns T 30ns 22.84s 210ns 22T T = 1/(fH x 2200/77) = 1.038s fH = HORIZONTAL SCAN FREQUENCY 1H Figure 95. High Definition (1080i) CGMS Waveform +700mV 70% 10% START BIT 1 BIT 2 CRC SEQUENCE BIT 134 H0 H1 H2 H3 H4 H5 P0 P1 P2 P3 P4 . . . P122 P123 P124 P125 P126 P127 0mV -300mV PLEASE REFERTO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION Figure 96. Enhanced Definition (525p) CGMS Type B Waveform +700mV 70% 10% START BIT 1 BIT 2 CRC SEQUENCE BIT 134 H0 H1 H2 H3 H4 H5 P0 P1 P2 P3 P4 . . . P122 P123 P124 P125 P126 P127 0mV -300mV PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION Figure 97. High Definition (720p and 1080i) CGMS Type B Waveform Rev. 0 | Page 71 of 88 06400-098 06400-097 06400-096 ADV7344 APPENDIX 2--SD WIDE SCREEN SIGNALING Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV7344 supports wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long. The function of each of these bits is shown in Table 55. Table 55. Function of WSS Bit Description Aspect Ratio, Format, Position 13 12 11 10 9 Bit Number 8765 4 3 1 0 0 1 0 1 1 0 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Setting 4:3, full format, N/A 14:9, letterbox, center 14:9, letterbox, top 16:9, letterbox, center 16:9, letterbox, top >16:9, letterbox, center 14:9, full format, center 16:0, N/A, N/A Camera mode Film mode Normal PAL Motion Adaptive ColorPlus Not present Present No Yes No Subtitles in active image area Subtitles out of active image area Reserved No Yes No copyright asserted or unknown Copyright asserted Copying not restricted Copying restricted The WSS data is preceded by a run-in sequence and a start code (see Figure 98). If SD WSS (Subaddress 0x99, Bit 7) is set to Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 sec from the falling edge of HSYNC) is available for the insertion of video. It is possible to blank the WSS portion of Line 23 with Subaddress 0xA1, Bit 7. Mode Color Encoding Helper Signals Reserved Teletext Subtitles Open Subtitles 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 Surround Sound Copyright Copy Protection 500mV RUN-IN SEQUENCE START CODE W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 ACTIVE VIDEO 11.0s 42.5s 06400-099 38.4s Figure 98. WSS Waveform Diagram Rev. 0 | Page 72 of 88 ADV7344 APPENDIX 3--SD CLOSED CAPTIONING Subaddress 0x91 to Subaddress 0x94 The ADV7344 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency- and phase-locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by the Logic 1 start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in the SD closed captioning registers (Subaddress 0x93 to Subaddress 0x94). The ADV7344 also supports the extended closed captioning operation, which is active during even fields and encoded on Scan Line 284. The data for this operation is stored in the SD closed captioning registers (Subaddress 0x91 to Subaddress 0x92). The ADV7344 automatically generates all clock run-in signals and timing that support closed captioning on Line 21 and Line 284. All pixels inputs are ignored on Line 21 and Line 284 if closed captioning is enabled. The FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA-608 describe the closed captioning information for Line 21 and Line 284. The ADV7344 uses a single buffering method. This means that the closed captioning buffer is only 1-byte deep. Therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. The data must be loaded one line before it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn loads the new data (2 bytes) in every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes, on Line 21. Otherwise, a TV does not recognize them. If there is a message such as "Hello World" that has an odd number of characters, it is important to add a blank character at the end to make sure that the end-of-caption, 2-byte control code lands in the same field. 10.5 0.25s 12.91s 7 CYCLES OF 0.5035MHz CLOCK RUN-IN TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A D0 TO D6 R T BYTE 0 P A R I T Y P A R I T Y 50 IRE D0 TO D6 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003s 27.382s BYTE 1 33.764s Figure 99. SD Closed Captioning Waveform, NTSC Rev. 0 | Page 73 of 88 06400-100 ADV7344 APPENDIX 4--INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS The ADV7344 is able to generate SD color bar and black bar test patterns. The register settings in Table 56 are used to generate an SD NTSC 75% color bar test pattern. CVBS output is available on DAC 4, S-Video (Y/C) output is on DAC 5 and DAC 6, and YPrPb output is on DAC 1 to DAC 3. Upon power-up, the subcarrier frequency registers default to the appropriate values for NTSC. All other registers are set as normal/default. Table 56. SD NTSC Color Bar Test Pattern Register Writes Subaddress 0x00 0x82 0x84 Setting 0xFC 0xC9 0x40 Note that when programming the FSC registers, the user must write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full FSC value to be written is accepted only after the FSC3 write is complete. ED/HD TEST PATTERNS The ADV7344 is able to generate ED/HD color bar, black bar, and hatch test patterns. The register settings in Table 58 are used to generate an ED 525p hatch test pattern. YPrPb output is available on DAC 1 to DAC 3. All other registers are set as normal/default. Table 58. ED 525p Hatch Test Pattern Register Writes Subaddress 0x00 0x01 0x31 Setting 0x1C 0x10 0x05 To generate an SD NTSC black bar test pattern, the same settings shown in Table 56 should be used with an additional write of 0x24 to Subaddress 0x02. For PAL output of either test pattern, the same settings are used, except that Subaddress 0x80 is programmed to 0x11 and the subcarrier frequency registers are programmed as shown in Table 57. Table 57. PAL FSC Register Writes Subaddress 0x8C 0x8D 0x8E 0x8F Description FSC0 FSC1 FSC2 FSC3 Setting 0xCB 0x8A 0x09 0x2A To generate an ED 525p black bar test pattern, the same settings as shown in Table 58 should be used with an additional write of 0x24 to Subaddress 0x02. To generate an ED 525p flat field test pattern, the same settings shown in Table 58 should be used, except that 0x0D should be written to Subaddress 0x31. The Y, Cr, and Cb levels for the hatch and flat field test patterns can be controlled using Subaddress 0x36, Subaddress 0x37, and Subaddress 0x38, respectively. For ED/HD standards other than 525p, the same settings as shown in Table 58 (and subsequent comments) are used except that Subaddress 0x30, Bits[7:3] are updated as appropriate. Rev. 0 | Page 74 of 88 ADV7344 APPENDIX 5--SD TIMING Mode 0 (CCIR-656)--Slave Option (Subaddress 0x8A = X X X X X 0 0 0) The ADV7344 is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. If the S_VSYNC and S_HSYNC pins are not used, they should be tied high during this mode. ANALOG VIDEO EAV CODE INPUT PIXELS C F00X818 1 Y Y r F00Y000 0 4 CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) 4 CLOCK END OF ACTIVE VIDEO LINE 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 CLOCK 280 CLOCK SAV CODE C C 8 1 8 1 F 0 0X CY C YC Y rYb b 0000F00Yb r 4 CLOCK 4 CLOCK 1440 CLOCK 1440 CLOCK 06400-101 START OF ACTIVE VIDEO LINE Figure 100. SD Slave Mode 0 Mode 0 (CCIR-656)--Master Option (Subaddress 0x8A = X X X X X 0 0 1) The ADV7344 generates H and F signals required for the SAV and EAV time codes in the CCIR656 standard. The H bit is output on S_HSYNC and the F bit is output on S_VSYNC. DISPLAY VERTICAL BLANK DISPLAY 522 H F 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 H F 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD Figure 101. SD Master Mode 0, NTSC Rev. 0 | Page 75 of 88 06400-102 ADV7344 DISPLAY VERTICAL BLANK DISPLAY 622 H 623 624 625 1 2 3 4 5 6 7 21 22 23 F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 309 H 310 311 312 313 314 315 316 317 318 319 320 334 335 336 F ODD FIELD EVEN FIELD Figure 102. SD Master Mode 0, PAL ANALOG VIDEO H F Figure 103. SD Master Mode 0, Data Transitions Mode 1--Slave Option (Subaddress 0x8A = X X X X X 0 1 0) In this mode, the ADV7344 accepts horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. HSYNC and FIELD are input on the S_HSYNC and S_VSYNC pins, respectively. DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 06400-104 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC FIELD 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 06400-103 ODD FIELD EVEN FIELD Figure 104. SD Slave Mode 1, NTSC Rev. 0 | Page 76 of 88 06400-105 ADV7344 DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 309 HSYNC FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 105. SD Slave Mode 1, PAL Mode 1--Master Option (Subaddress 0x8A = X X X X X 0 1 1) In this mode, the ADV7344 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the S_HSYNC and S_VSYNC pins, respectively. HSYNC FIELD PIXEL DATA Cb Y Cr Y 06400-107 PAL = 132 x CLOCK/2 NTSC = 122 x CLOCK/2 Figure 106. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave) Mode 2-- Slave Option (Subaddress 0x8A = X X X X X 1 0 0) In this mode, the ADV7344 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the S_HSYNC and S_VSYNC pins, respectively. Rev. 0 | Page 77 of 88 06400-106 ADV7344 DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC VSYNC 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD DISPLAY ODD FIELD DISPLAY VERTICAL BLANK 260 HSYNC VSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD Figure 107. SD Slave Mode 2, NTSC DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC VSYNC 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD DISPLAY ODD FIELD DISPLAY VERTICAL BLANK 309 HSYNC VSYNC 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 108. SD Slave Mode 2, PAL Mode 2--Master Option (Subaddress 0x8A = X X X X X 1 0 1) In this mode, the ADV7344 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are output on the S_HSYNC and S_VSYNC pins, respectively. HSYNC VSYNC PIXEL DATA PAL = 132 x CLOCK/2 NTSC = 122 x CLOCK/2 Cb Y Cr Y 06400-110 Figure 109. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave) Rev. 0 | Page 78 of 88 06400-109 06400-108 ADV7344 HSYNC VSYNC PAL = 864 x CLOCK/2 NTSC = 858 x CLOCK/2 PIXEL DATA PAL = 132 x CLOCK/2 NTSC = 122 x CLOCK/2 Cb Y Cr Y Cb 06400-111 Figure 110. SD Timing Mode 2 Odd-to-Even Field Transition (Master/Slave) Mode 3--Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode, the ADV7344 accepts or generates horizontal sync and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are output in master mode and input in slave mode on the S_VSYNC and S_VSYNC pins, respectively. DISPLAY DISPLAY VERTICAL BLANK 522 HSYNC FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD DISPLAY ODD FIELD DISPLAY VERTICAL BLANK 260 HSYNC FIELD 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD Figure 111. SD Timing Mode 3, NTSC DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD DISPLAY ODD FIELD DISPLAY VERTICAL BLANK 309 HSYNC FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 EVEN FIELD ODD FIELD Figure 112. SD Timing Mode 3, PAL Rev. 0 | Page 79 of 88 06400-113 06400-112 ADV7344 APPENDIX 6--HD TIMING DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL 1124 P_VSYNC 1125 1 2 3 4 5 6 7 8 20 21 22 560 P_HSYNC DISPLAY FIELD 2 VERTICAL BLANKING INTERVAL 561 P_VSYNC 562 563 564 565 566 567 568 569 570 583 584 585 1123 P_HSYNC Figure 113. 1080i HSYNC and VSYNC Input Timing Rev. 0 | Page 80 of 88 06400-114 ADV7344 APPENDIX 7--VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS--SMPTE/EBU N10 Pattern: 100% Color Bars MAGENTA YELLOW MAGENTA YELLOW GREEN GREEN BLACK WHITE CYAN BLUE RED BLACK BLACK BLACK 06400-120 06400-119 06400-118 WHITE CYAN 700mV 700mV 300mV 06400-115 300mV Figure 114. Y Levels--NTSC Figure 117. Y Levels--PAL MAGENTA YELLOW GREEN BLACK MAGENTA YELLOW GREEN WHITE CYAN WHITE CYAN BLUE RED 700mV 700mV 06400-116 Figure 115. Pr Levels--NTSC Figure 118. Pr Levels--PAL MAGENTA YELLOW GREEN BLACK MAGENTA YELLOW GREEN WHITE CYAN WHITE CYAN BLUE RED 700mV 700mV 06400-117 Figure 116. Pb Levels--NTSC Figure 119. Pb Levels--PAL Rev. 0 | Page 81 of 88 BLUE RED BLUE RED BLUE RED ADV7344 ED/HD YPRPB OUTPUT LEVELS INPUT CODE 940 EIA-770.2, STANDARD FOR Y INPUT CODE 940 EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE OUTPUT VOLTAGE 700mV 700mV 64 64 300mV 300mV EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE EIA-770.2, STANDARD FOR Pr/Pb 960 OUTPUT VOLTAGE 960 600mV 512 512 700mV 700mV 06400-123 64 06400-121 64 Figure 122. EIA-770.3 Standard Output Signals (1080i/720p) Figure 120. EIA-770.2 Standard Output Signals (525p/625p) INPUT CODE INPUT CODE 940 EIA-770.1, STANDARD FOR Y OUTPUT VOLTAGE 782mV Y-OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE 1023 700mV 714mV 64 64 286mV 300mV INPUT CODE EIA-770.1, STANDARD FOR Pr/Pb 960 OUTPUT VOLTAGE Pr/Pb-OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE 1023 700mV 512 700mV 64 06400-122 300mV 64 Figure 121. EIA-770.1 Standard Output Signals (525p/625p) Figure 123. Output Levels for Full Input Selection Rev. 0 | Page 82 of 88 06400-124 ADV7344 SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R 700mV/525mV R 700mV/525mV 300mV 300mV G 700mV/525mV G 700mV/525mV 300mV 300mV B 700mV/525mV 06400-125 B 700mV/525mV 06400-127 300mV 300mV Figure 124. SD/ED RGB Output Levels--RGB Sync Disabled Figure 126. HD RGB Output Levels--RGB Sync Disabled R R 700mV/525mV 700mV/525mV 600mV 300mV 300mV 0mV 0mV G G 700mV/525mV 700mV/525mV 600mV 300mV 300mV 0mV 0mV B B 700mV/525mV 700mV/525mV 600mV 300mV 06400-126 300mV 06400-128 0mV 0mV Figure 125. SD/ED RGB Output Levels--RGB Sync Enabled Figure 127. HD RGB Output Levels--RGB Sync Enabled Rev. 0 | Page 83 of 88 ADV7344 SD OUTPUT PLOTS VOLTS IRE:FLT VOLTS 0.6 100 0.4 0.5 50 0.2 0 0 0 -0.2 -50 0 10 F1 L76 20 L608 0 10 20 30 40 50 60 MICROSECONDS NOISE REDUCTION: 0.00dB APL = 39.1% PRECISION MODE OFF 625 LINE NTSC NO FILTERING SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1, 2, 3, 4 SLOW CLAMP TO 0.00 AT 6.72s 06400-129 Figure 128. NTSC Color Bars (75%) Figure 131. PAL Color Bars (75%) VOLTS IRE:FLT 0.6 VOLTS 0.5 0.4 50 0.2 0 0 0 0 -0.2 0 10 F2 L238 20 0 10 L575 20 30 40 50 60 70 06400-130 Figure 129. NTSC Luma Figure 132. PAL Luma VOLTS IRE:FLT 0.4 50 VOLTS 0.5 0.2 0 0 0 -0.2 -50 -0.4 F1 L76 30 40 50 60 MICROSECONDS NOISE REDUCTION: 15.05dB PRECISION MODE OFF APL NEEDS SYNC SOURCE. SYNCHRONOUS SYNC = B 525 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00 AT 6.72s 0 10 20 -0.5 L575 30 40 50 60 MICROSECONDS APL NEEDS SYNC SOURCE. NO BUNCH SIGNAL 625 LINE PAL NO FILTERING PRECISION MODE OFF SLOW CLAMP TO 0.00 AT 6.72s SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1 0 10 20 06400-131 Figure 130. NTSC Chroma Figure 133. PAL Chroma Rev. 0 | Page 84 of 88 06400-134 06400-133 30 40 50 60 MICROSECONDS NOISE REDUCTION: 15.05dB APL = 44.3% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = SOURCE SLOW CLAMP TO 0.00V AT 6.72s FRAMES SELECTED 1, 2 MICROSECONDS APL NEEDS SYNC SOURCE. NO BUNCH SIGNAL 625 LINE PAL NO FILTERING PRECISION MODE OFF SLOW CLAMP TO 0.00 AT 6.72s SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1 06400-132 30 40 50 60 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72s FRAMES SELECTED 1, 2 ADV7344 APPENDIX 8--VIDEO STANDARDS 0HDATUM SMPTE 274M ANALOG WAVEFORM DIGITAL HORIZONTAL BLANKING *1 4T EAV CODE INPUT PIXELS F F 00F 00V H* 4 CLOCK SAMPLE NUMBER 2112 2116 2156 0 2199 44 188 272T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE 4T SAV CODE 1920T DIGITAL ACTIVE LINE CY r F 0 0F C C V F 0 0 H* b Y r 4 CLOCK 192 2111 FOR A FRAME RATE OF 30Hz: 40 SAMPLES FOR A FRAME RATE OF 25Hz: 480 SAMPLES Figure 134. EAV/SAV Input Data Timing Diagram (SMPTE 274M) SMPTE 293M ANALOG WAVEFORM EAV CODE INPUT PIXELS F F00V F 0 0 H* 4 CLOCK SAMPLE NUMBER 719 723 736 0HDATUM 799 DIGITAL HORIZONTAL BLANKING FVH* = FVH AND PARITY BITS SAV: LINE 43 TO 525 = 200H SAV: LINE 1 TO 42 = 2AC EAV: LINE 43 TO 525 = 274H EAV: LINE 1 TO 42 = 2D8 ANCILLARY DATA (OPTIONAL) SAV CODE F 0 0F V F 0 0 H* 4 CLOCK 853 857 0 719 DIGITAL ACTIVE LINE C C bYr C YrY Figure 135. EAV/SAV Input Data Timing Diagram (SMPTE 293M) ACTIVE VIDEO VERTICAL BLANK ACTIVE VIDEO 522 523 524 525 1 2 5 6 7 8 9 12 13 14 15 16 42 43 44 Figure 136. SMPTE 293M (525p) Rev. 0 | Page 85 of 88 06400-137 06400-136 06400-135 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1 TO 562: F = 0 SAV/EAV: LINE 563 TO 1125: F = 1 SAV/EAV: LINE 1 TO 20; 561 TO 583; 1124 TO 1125: V = 1 SAV/EAV: LINE 21 TO 560; 584 TO 1123: V = 0 ADV7344 ACTIVE VIDEO VERTICAL BLANK ACTIVE VIDEO 622 623 624 625 1 2 4 5 6 7 8 9 10 11 12 13 43 44 45 Figure 137. ITU-R BT.1358 (625p) DISPLAY VERTICAL BLANKING INTERVAL 06400-138 06400-140 06400-139 747 748 749 750 1 2 3 4 5 6 7 8 25 26 27 744 745 Figure 138. SMPTE 296M (720p) DISPLAY VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 DISPLAY VERTICAL BLANKING INTERVAL FIELD 2 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 Figure 139. SMPTE 274M (1080i) Rev. 0 | Page 86 of 88 ADV7344 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 1 PIN 1 12.20 12.00 SQ 11.80 64 49 48 TOP VIEW (PINS DOWN) 10.20 10.00 SQ 9.80 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 COPLANARITY 16 17 32 33 VIEW A VIEW A ROTATED 90 CCW 0.50 BSC LEAD PITCH 0.27 0.22 0.17 051706-A COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 140. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model ADV7344BSTZ 2 EVAL-ADV7344EBZ2 1 2 Temperature Range -40C to +85C Macrovision 1 Antitaping Yes Yes Package Description 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Platform Package Option ST-64-2 Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video. Z = Pb-free. Rev. 0 | Page 87 of 88 ADV7344 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06400-0-10/06(0) Rev. 0 | Page 88 of 88 |
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